SL2309
Switching Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades
Symbol
Description
Condition
Min
Typ
Max
Unit
FMAX1
Maximum Frequency [1]
(Input=Output )
High drive (-1H). All outputs CL=15pF
High drive (-1H), All outputs CL=30pF
Standard drive, (-1), All outputs CL=15pf
10
10
10
10
0
–
–
140
100
100
66
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
All Active PLL Modes
–
Standard drive, (-1), All outputs CL=30pf
High drive (-1H). All outputs CL=15pF
–
FMAX2
Maximum Frequency [1]
(Input=Output )
–
140
100
100
66
High drive (-1H), All outputs CL=30pF
Standard drive, (-1), All outputs CL=15pf
0
–
PLL Bypass Mode
(S2=1 and S1=0)
0
–
Standard drive, (-1), All outputs CL=30pf
Measured at 1.4V, Fout=66MHz, CL=15pF
Measured at 1.4V, Fout=66MHz, CL=15pF
High drive (-1H), CL=15pF
0
–
Input Duty Cycle
INDC
30
40
–
50
50
–
70
OUTDC
Output Duty Cycle[2]
60
%
tr/f
Rise, Fall Time (3.3V) [2]
(Measured at: 0.8 to 2.0V)
1.5
1.8
2.2
2.5
ns
High drive (-1H), CL=30pF
–
–
ns
Standard drive (-1), CL=15pF
–
–
ns
Standard drive (-1), CL=30pF
–
–
ns
t1
t2
t3
Output-to-Output Skew[2]
(Measured at VDD/2)
Device-to-Device Skew[2]
All outputs CL=0 or equally loaded, -1 or
-1H drives
–
–
50
150
5
120
400
8.7
ps
ps
ns
ps
ms
All outputs CL=0 or equally loaded, -1 or
-1H drives
(Measured at VDD/2)
Delay Time, CLKIN Rising
Edge to CLKOUT Rising
Edge[2]
PLL Bypass mode
1.5
–150
–
Only when S2=1 and S1=0
PLL enabled
(Measured at VDD/2)
–
150
1.0
All active PLL modes
tPLOCK PLL Lock Time[2]
Time from 90% of VDD to valid clocks on
all the output clocks
–
CCJ
Cycle-to-cycle Jitter [2]
Fin=Fout=66 MHz, <CL=15pF, -1H drive
Fin=Fout=66 MHz, <CL=15pF, -1 drive
Fin=Fout=66 MHz, <CL=30pF, -1H drive
Fin=Fout=66 MHz, <CL=30pF, -1 drive
–
–
–
–
50
60
65
75
100
120
130
150
ps
ps
ps
ps
Notes:
1. For the given maximum loading conditions. See CL in Operating Conditions Table.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Rev 1.1, May 29, 2007
Page 7 of 12
SPECTRALINEAR [ SPECTRALINEAR INC ]
