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SL15300ZI-XXX 参数 Datasheet PDF下载

SL15300ZI-XXX图片预览
型号: SL15300ZI-XXX
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程扩频时钟发生器( SSCG ) [Programmable Spread Spectrum Clock Generator (SSCG)]
分类和应用: 时钟发生器
文件页数/大小: 16 页 / 368 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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SL15300  
tr/f5  
tr/f6  
Programmable, VDD=2.5  
Output Rise/Fall Time  
Output Rise/Fall Time  
Output Rise/Fall Time  
-
-
1.10  
0.90  
1.35  
1.10  
ns  
ns  
CL=15pF, 20 to 80% of VDD  
Programmable, VDD=2.5  
CL=15pF, 20 to 80% of VDD  
tr/f7  
Programmable, VDD=2.5  
-
-
0.70  
TBD  
0.85  
TBD  
ns  
ps  
CL=15pF, 20 to 80% of VDD  
Cycle-to-Cycle Jitter  
CCJ1  
CCJ2  
FIN=30MHz, all 4 clocks are at  
33MHz, +/-2.0% Spread. CL=15pF  
(SSCLK – Pins 4/6/7/8 )  
Cycle-to-Cycle Jitter  
FIN=30MHz, all 4 clocks are at  
-
TBD  
TBD  
ps  
33MHz, +/-2.0% Spread. CL=15pF  
(SSCLK – Pins 4/6/7/8)  
tPD  
tPU  
Time from PD# falling edge to Hi-Z  
at outputs (Asynchronous)  
-
-
150  
3.5  
350  
5.0  
ns  
Power-down Time  
Time from PD# rising edge to valid  
frequency at outputs  
(Asynchronous)  
ms  
Power-up Time  
(Crystal or Clock)  
tPSR  
Time for VDD reaching minimum  
specified value and monolithic  
power supply ramp  
-
-
12  
ms  
Power Supply Ramp  
Time  
tOE  
tOD  
Time from OE falling edge to Hi-Z at  
outputs (Asynchronous)  
-
-
180  
180  
350  
350  
ns  
ns  
Output Enable Time  
Output Disable Time  
Time from OE falling edge to Hi-Z at  
outputs (Asynchronous)  
Spread Percent Range  
Spread Percent Range  
Spread Percent Variation  
Modulation Frequency  
SPR-1  
SPR-2  
ΔSS%  
FMOD  
Center Spread, SSCLK-1/2/3/4  
Down Spread, SSCLK-1/2/3/4  
Variation of programmed Spread %  
Programmable, 31.5 kHz standard  
+/-0.125  
-5.0  
-
+/-2.5  
-0.25  
15  
%
%
-
-
-15  
%
25  
31.5  
120  
kHz  
DC Electrical Characteristics (I-Grade)  
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C  
Description  
Symbol  
Condition  
VDD+/-10%  
Min  
Typ  
Max  
Unit  
Operating Voltage  
VDD  
2.97  
3.3  
3.63  
V
CMOS Level, if Pins 4 and 8  
programmed as PD#, OE,  
SSON# or FS  
Input Low Voltage  
Input High Voltage  
Output High Voltage  
Output Low Voltage  
VIL  
VIH  
0
-
-
-
-
0.3VDD  
VDD  
-
V
CMOS Level, if Pins 4 and 8  
programmed as PD#, OE,  
SSON# or FS.  
0.7VDD  
VDD-0.5  
-
V
V
V
IOH=10mA , If Pins 4, 6, 7 and  
8 are programmed as  
SSCLK/REFCLK  
VOH1  
VOL1  
IOL=10mA, If Pins 4, 6, 7 and 8  
are programmed as  
0.5  
SSCLK/REFCLK  
Rev 1.0, August 14, 2008  
Page 8 of 16