CY2SSTV857-27
Yx
tC(n)
tC(n+1)
Figure 3. Cycle-to-cycle Jitter
= 2.5"
= 0.6" (Split to Terminator)
DDR _SDRAM
represents a capacitive load
CLK
PLL
120
Ohm
DDR -
SDRAM
CLK#
VTR
VCP
120
Ohm
FBIN
120
Ohm
DDR -
SDRAM
FBIN#
FBOUT
FBOUT#
0.3"
Output load capacitance for 2 DDR-SDRAM Loads: 5 pF< CL< 8 pF
Figure 4. Clock Structure # 1
= 2.5"
= 0.6" (Split to Terminator)
DDR-SDRAM
represents a capacitive load
DDR-SDRAM
DDR-SDRAM
DDR-SDRAM
Stack
CLK
PLL
120 Ohm
CLK#
VTR
VCP
120 Ohm
FBIN
120 Ohm
DDR-SDRAM
DDR-SDRAM
Stack
FBIN#
FBOUT
FBOUT#
DDR-SDRAM
0.3"
Output load capacitancce for 4 DDR-SDRAM Loads: 10 pF < CL < 16 pF
Figure 5. Clock Structure # 1
Rev 1.0,November 21, 2006
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