CY2SSTV855
Absolute Maximum Conditions[3]
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, Vin and Vout should be constrained to the
range:
Input Voltage Relative to VSS:...............................VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V
Storage Temperature: ................................ –65qC to + 150qC
Operating Temperature:................................ –40qC to +85qC
Maximum Power Supply:................................................3.5V
VSS < (Vin or Vout) < VDD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Electrical Specifications (AVDD = VDDQ = 2.5V 5%, TA = –40°C to +85°C)[4]
Parameter
VID
Description
Conditions
CLKINT, FBINT
Min.
Typ.
Max.
Unit
V
Differential Input Voltage[5]
0.36
VDDQ + 0.6
VIX
Differential Input Crossing Voltage[6] CLKTIN, FBINT
(VDDQ/2)– VDDQ/2 (VDDQ/2) +
V
0.2
0.2
IIN
Input Current
VIN = 0V or VIN = VDDQ, CLKINT,
FBINT
–10
–
10
µA
IOL
Output Low Current
Output High Current
Output Low Voltage
Output High Voltage
Output Voltage Swing[7]
Output Crossing Voltage[8]
VDDQ = 2.375V, VOUT = 1.2V
VDDQ = 2.375V, VOUT = 1V
VDDQ = 2.375V, IOL = 12 mA
VDDQ = 2.375V, IOH = –12 mA
26
35
–32
–
–
mA
mA
V
IOH
–18
–
VOL
VOH
VOUT
VOC
0.6
–
1.7
1.1
–
V
–
VDDQ – 0.4
V
(VDDQ/2) – VDDQ/2 (VDDQ/2) +
V
0.2
–10
–
0.2
10
300
12
–
IOZ
High-Impedance Output Current
Dynamic Supply Current[9]
PLL Supply Current
VO = GND or VO = VDDQ
VDDQ = 170 MHz
AVDD only
µA
mA
mA
pF
IDDQ
IDD
235
9
–
Cin
Input Pin Capacitance
–
4
AC Electrical Specifications (AVDD = VDDQ = 2.5V 5%, TA = –40°C to +85°C)[10, 11]
Parameter
fCLK
Description
Conditions
Min.
60
Typ.
Max.
170
60
Unit
MHz
%
Operating Clock Frequency
Input Clock Duty Cycle[12]
Maximum PLL lock Time
AVDD = 2.5V r 0.2V
tDC
40
tLOCK
100
2
µs
tSL(O)
Output Clocks Slew Rate
Output Enable Time (all outputs)[13]
Output Disable Time (all outputs)[13]
Cycle to Cycle Jitter
20% to 80% of VOD
1
V/ns
ns
tPZL, tPZH
tPLZ, tPHZ
tCCJ
30
10
ns
f > 66 MHz
f > 66 MHz
–100
–100
100
100
ps
tJITT(H-PER) Half-period jitter
ps
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. Unused inputs must be held HIGH or LOW to prevent them from floating.
5. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the comple-
mentary input level.
6. Differential cross-point input voltage is expected to track V
7. For load conditions see Figure 6.
and is the voltage at which the differential signals must be crossing.
DDQ
8. The value of V is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120: resistor. See Figure 6.
OC
9. All outputs switching loaded with 16 pF in 60: environment. See Figure 6.
10. Parameters are guaranteed by design and characterization. Not 100% tested in production.
11. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a
downspread of –0.5%
12. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = t /t ,
C
WH
where the cycle time (t ) decreases as the frequency goes up.
C
13. Refers to transition of non-inverting output.
14. All differential input and output terminals are terminated with 120:/16 pF as shown in Figure 6.
Rev 1.0,November 21, 2006
Page 5 of 6
SPECTRALINEAR [ SPECTRALINEAR INC ]
