CY2SSTV16859
DC Electrical Specifications (continued)
Parameter
Description
Dynamic
operating–clock CLK and CLK# switching 50% duty
Condition
VDD
Min.
Typ.[9] Max. Unit
IDDD
RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0
2.7V
–
30.0
–
µA/
clock
MHz
only
cycle
Dynamic
RESET# = VDD, VI = VIH(AC) or VIL(AC),
2.7
–
15.0
–
µA/
operating – per CLK and CLK# switching 50% duty
each data input cycle. One data input switching at half
clock frequency, 50% duty cycles.
clock
MHz
/data
input
rOH
rOL
Output high
Output low
IOH = –20 mA
IOL = 20 mA
2.3 to 2.7V
2.3 to 2.7V
2.5V
7
7
–
–
–
–
20
20
4
:
:
:
rO(')
|rOH – rOL| each IO = 20 mA, TA = 25°C
separate bit
Ci
Data Inputs
CLK and CLK#
RESET#
VI = VREF + 310 mV
ICR = 1.25V, VI(PP) = 360 mV
VI = VDD or VSS
2.5
2.5
2.5
2.5
2.5
2.5
–
–
–
3.5
3.5
3.5
pF
pF
pF
V
AC Electrical Specifications
VDD = 2.5V 0.2V
Parameter
Description
Min.
–
Max.
280
–
Unit
fclock
tw
Clock Frequency
Pulse duration, CLK, CLK# high or low
MHz
ns
2.0
–
tact
Differential inputs active time (data inputs must be held low after RESET# is taken high).
22
ns
tinact
Differential inputs inactive time (data and clock inputs must be held at valid levels
(not floating) after RESET# is taken low).
–
22
ns
tsu
Set-up time, fast slew rate[10, 12]
Set-up time, slow slew rate[11, 12]
Hold time, fast slew rate[10, 12]
Hold time, slow slew rate[11, 12]
Data before CLKn, CLK#p
0.75
0.9
–
–
–
–
ns
ns
ns
ns
th
Data after CLK n, CLK#p
0.75
0.9
Table 2. Switching Characteristics Over Recommended Operating Conditions[13]
Parameter
From (Input)
To (Output)
VDD = 2.5V 0.2V
Unit
Min.
Max.
–
fmax
tPHL
280
MHz
ns
RESET#
CLK and CLK#
Q
Q
5
tPD
1.1
2.8
ns
Notes:
10. For data signal input slew rate tꢀꢁꢀV/ns.
11. For data signal input slew rate t V/ns and ꢂꢀꢁV/ns.
12. CLK and CLK# signals input slew rates are tꢀ1 V/ns.
13. See test circuits and waveforms. TA = 0°C to +85°C.
Rev 1.0,November 21, 2006
Page 4 of 7
SPECTRALINEAR [ SPECTRALINEAR INC ]
