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CY28RS400ZXCT 参数 Datasheet PDF下载

CY28RS400ZXCT图片预览
型号: CY28RS400ZXCT
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟发生器为ATI RS400芯片组 [Clock Generator for ATI RS400 Chipset]
分类和应用: 晶体时钟发生器外围集成电路光电二极管
文件页数/大小: 18 页 / 179 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28RS400  
Crystal Recommendations  
The CY28RS400 requires a Parallel Resonance Crystal.  
Substituting a series resonance crystal will cause the  
CY28RS400 to operate at the wrong frequency and violate the  
ppm specification. For most applications there is a 300-ppm  
frequency shift between series and parallel crystals due to  
incorrect loading.  
Table 6. Crystal Recommendations  
Frequency  
(Fund)  
Drive  
(max.)  
Shunt Cap Motional  
(max.)  
Tolerance  
(max.)  
Stability  
(max.)  
Aging  
(max.)  
Cut  
Loading Load Cap  
Parallel 20 pF  
(max.)  
14.31818 MHz  
AT  
0.1 mW  
5 pF  
0.016 pF  
35 ppm  
30 ppm  
5 ppm  
The following diagram shows a typical crystal configuration  
using the two trim capacitors. An important clarification for the  
following discussion is that the trim capacitors are in series  
with the crystal not parallel. It’s a common misconception that  
load capacitors are in parallel with the crystal and should be  
approximately equal to the load capacitance of the crystal.  
This is not true.  
Crystal Loading  
Crystal loading plays a critical role in achieving low ppm perfor-  
mance. To realize low ppm performance, the total capacitance  
the crystal will see must be considered to calculate the appro-  
priate capacitive loading (CL).  
Figure 1. Crystal Capacitive Clarification  
crystal. This means the total capacitance on each side of the  
crystal must be twice the specified crystal load capacitance  
(CL). While the capacitance on each side of the crystal is in  
series with the crystal, trim capacitors (Ce1,Ce2) should be  
calculated to provide equal capacitive loading on both sides.  
Calculating Load Capacitors  
In addition to the standard external trim capacitors, trace  
capacitance and pin capacitance must also be considered to  
correctly calculate crystal loading. As mentioned previously,  
the capacitance on each side of the crystal is in series with the  
Clock Chip  
Ci2  
Ci1  
Pin  
3 to 6p  
X2  
X1  
Cs2  
Cs1  
Trace  
2.8pF  
XTAL  
Ce1  
Ce2  
Trim  
33pF  
Figure 2. Crystal Loading Example  
Rev 1.0,November 22, 2006  
Page 8 of 18