CY28RS400
Byte 5: Control Register 5 (continued)
Bit
@Pup
Name
Description
SRC[T/C]3 CLKREQ#1 control
5
0
SRC[T/C]3
1 = SRC[T/C]3 stoppable by CLKREQ#1 pin
0 = SRC[T/C]3 free running
4
3
2
0
0
0
SRC[T/C]2
SRC[T/C]1
SRC[T/C]0
SRC[T/C]2 CLKREQ#1 control
1 = SRC[T/C]2 stoppable by CLKREQ#1 pin
0 = SRC[T/C]2 free running
SRC[T/C]1 CLKREQ#1 control
1 = SRC[T/C]1 stoppable by CLKREQ#1 pin
0 = SRC[T/C]1 free running
SRC[T/C]0 CLKREQ#1 control
1 = SRC[T/C]1 stoppable by CLKREQ#1 pin
0 = SRC[T/C]1 free running
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
TEST_SEL
REF/N or Tri-state Select
1 = REF/N Clock, 0 = Tri-state
6
5
0
0
TEST_MODE
REF
Test Clock Mode Entry Control
1 = REF/N or Tri-state mode, 0 = Normal operation
REF output drive strength.
0 = Low drive, 1 = High drive.
4
3
0
Reserved
409_410
Reserved
HW
409_410 reflects the value of the 409_410 pin sampled on power up. 0 =
409_410 was low during VTT_PWRGD# assertion
2
1
0
HW
HW
HW
FS_C
FS_B
FS_A
FS_C Reflects the value of the FS_C pin sampled on power up. 0 = FS_C
was low during VTT_PWRGD# assertion.
FS_B Reflects the value of the FS_B pin sampled on power up. 0 = FS_B
was low during VTT_PWRGD# assertion.
FS_A Reflects the value of the FS_A pin sampled on power up. 0 = FS_A
was low during VTT_PWRGD# assertion.
Byte 7: Vendor ID
Bit
7
@Pup
Name
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
0
0
0
1
1
0
0
0
6
5
4
3
2
Vendor ID Bit 2
1
Vendor ID Bit 1
0
Vendor ID Bit 0
Rev 1.0,November 22, 2006
Page 7 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
