CY28435
Byte 2: Control Register 2 (continued)
Bit
@Pup
Name
Description
Description
0
1
PCIF1
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Byte 3: Control Register 3
Bit
@Pup
Name
7
0
SRC[T/C]7
Allow control of SRC[T/C]7 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
6
5
4
3
2
1
0
0
0
0
0
0
0
0
SRC[T/C]6
SRC[T/C]5
Allow control of SRC[T/C]6 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]5 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
SRC[T/C]4_SATA
SRC[T/C]3
Allow control of SRC[T/C]4_SATA with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]3 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
SRC[T/C]2
Allow control of SRC[T/C]2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
SRC[T/C]1
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
RESERVED
RESERVED, Set = 0
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
HW
FS_E
FS_E Reflects the value of the FS_E pin sampled on power-up. 0 = FS_E
was LOW during VTT_PWRGD# assertion.
6
5
4
3
0
0
0
0
DOT96[T/C]
PCIF2
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
Allow control of PCIF2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
PCIF1
Allow control of PCIF1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
PCIF0
Allow control of PCIF0 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2
1
0
1
1
1
RESERVED
RESERVED
RESERVED
RESERVED, Set = 1
RESERVED, Set = 1
RESERVED, Set = 1
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
SRC[T/C]
SRC[T/C] Stop Drive Mode
0 = Driven when SW PCI_STP# asserted,1 = Tri-state when SW
PCI_STP# asserted
6
5
4
3
0
0
0
0
RESERVED
RESERVED
RESERVED
SRC[T/C][7:1]
RESERVED, Set = 0
RESERVED, Set = 0
RESERVED, Set = 0
SRC[T/C][7:1] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
2
1
0
0
RESERVED
CPU[T/C]1
RESERVED, Set = 0
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
Rev 1.0,November 20, 2006
Page 6 of 22
SPECTRALINEAR [ SPECTRALINEAR INC ]
