CY28411
Pin Definitions
Pin No.
Name
CPU_STP#
Type
Description
54
I, PU 3.3V LVTTL input for CPU_STP# active low.
O, DIF Differential CPU clock outputs.
44,43,41,40 CPUT/C
36,35
CPUT2_ITP/SRCT7, O, DIF Selectable differential CPU or SRC clock output.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
CPUC2_ITP/SRCC7
14,15
12
DOT96T, DOT96C
FS_A/USB_48
O, DIF Fixed 96 MHz clock output.
I/O, SE 3.3V-tolerant input for CPU frequency selection/fixed 48 MHz clock output.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
16
53
39
FS_B/TEST_MODE
FS_C/TEST_SEL
IREF
I
I
I
3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Hi-Z when
in test mode
0 = Hi-Z, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
3.3V-tolerant input for CPU frequency selection. Selects test mode if pulled
to VIMFS_C when VTT_PWRGD# is asserted low.
Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifi-
cations.
A precision resistor is attached to this pin, which is connected to the internal
current reference.
56,3,4,5
PCI
O, SE 33 MHz clocks.
55
8
PCI_STP#
PCIF0/ITP_EN
I, PU 3.3V LVTTL input for PCI_STP# active low.
I/O, SE 33 MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC7
9
PCIF1
REF
O, SE 33 MHz clocks.
52
O, SE Reference clock. 3.3V 14.318-MHz clock output.
46
SCLK
SDATA
I
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
47
I/O
26,27
SRC4_SATAT,
SRC4_SATAC
O, DIF Differential serial reference clock. Recommended output for SATA.
24,25,22,23, SRCT/C
19,20,17,18,
33,32,31,30
O, DIF Differential serial reference clocks.
11
VDD_48
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for PLL.
GND Ground for outputs.
42
VDD_CPU
VDD_PCI
VDD_REF
VDD_SRC
VDDA
1,7
48
21,28,34
37
13
VSS_48
45
VSS_CPU
VSS_PCI
VSS_REF
VSS_SRC
VSSA
GND Ground for outputs.
2,6
51
GND Ground for outputs.
GND Ground for outputs.
29
GND Ground for outputs.
38
GND Ground for PLL.
10
VTT_PWRGD#/PD
I, PU 3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A,
FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD#
(active low) assertion, this pin becomes a real-time input for asserting power
down (active high).
50
49
XIN
I
14.318 MHz crystal input.
XOUT
O, SE 14.318 MHz crystal output.
Rev 1.0,November 22, 2006
Page 2 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
