CY28411-1
Byte 0:Control Register 0 (continued)
Bit
@Pup
Name
Description
2
1
SRC[T/C]2
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
1
0
1
1
SRC[T/C]1
SRC[T/C]0
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
1
PCIF0
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
6
5
4
1
1
1
DOT_96T/C
USB_48
REF
DOT_96 MHz Output Enable
0 = Disable (Hi-Z), 1 = Enabled
USB_48 MHz Output Enable
0 = Disabled, 1 = Enabled
REF Output Enable
0 = Disabled, 1 = Enabled
3
2
0
1
Reserved
Reserved
CPU[T/C]1
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
1
0
1
0
CPU[T/C]0
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
CPUT/C
SRCT/C
PCIF
Spread Spectrum Enable
0 = Spread off, 1 = Spread on
PCI
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
PCI5
PCI5 Output Enable
0 = Disabled, 1 = Enabled
6
5
4
1
1
1
PCI4
PCI3
PCI2
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
3
2
1
0
1
1
1
1
Reserved
Reserved
Reserved
PCIF1
Reserved, Set = 1
Reserved, Set = 1
Reserved, Set = 1
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
0
SRC7
Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
6
5
0
0
SRC6
SRC5
Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Rev 1.0,November 22, 2006
Page 5 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
