CY28409
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
1
CLe
=
1
Ce2 + Cs2 + Ci2
1
Ce1 + Cs1 + Ci1
(
)
+
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
C lo ck C h ip
(C Y 2 8 4 0 9 )
Ce..................................................... External trim capacitors
Cs..............................................Stray capacitance (terraced)
C i2
C i1
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
P in
3 to 6 p
PD# (Power-down) Clarification
X 2
The PD# (Power-down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is LOW, all clocks are driven to a LOW value and held there
and the VCO and PLLs are also powered down. All clocks are
shut down in a synchronous manner so as not to cause
glitches while changing to the low ‘stopped’ state.
X 1
C s2
C s1
T ra ce
2 .8 p F
X T A L
C e 1
C e 2
T rim
3 3 p F
Figure 2. Crystal Loading Example
PD# Assertion
When PD# is sampled LOW by two consecutive rising edges
of the CPUC clock then all clock outputs (except CPU) clocks
must be held LOW on their next HIGH-to-LOW transition. CPU
clocks must be held with CPU clock pin driven HIGH with a
value of 2 x Iref and CPUC undriven. Due to the state of
internal logic, stopping and holding the REF clock outputs in
the LOW state may require more than one clock cycle to
complete
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF
Figure 3. Power-down Assertion Timing Waveform
Rev 1.0,November 22, 2006
Page 8 of 16
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