CY28401
Byte 0: Control Register 0 (continued)
Bit
5
@pup
Name
Description
0
0
0
1
Reserved
Reserved
Reserved
HIGH_BW#
4
3
2
0 = High Bandwidth, 1 = Low bandwidth
1
0
1
1
PLL/Bypass#
0 = Fanout buffer, 1 = PLL mode
SRC_DIV/2
0 = Divided by 2 mode, 1 = Normal (output = input)
Byte 1: Control Register 1
Bit
@pup
Name
Description
7
1
DIF_7 Output Enable
0 = Disabled (three-state)
1 = Enabled
6
5
4
3
2
1
0
1
1
1
1
1
1
1
DIF_6 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_5 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_4 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_3 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_2 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_1 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_0 Output Enable
0 = Disabled (three-state)
1 = Enabled
Byte 2: Control Register 2
Bit
@pup
Name
Description
7
0
Allow Control DIF_7 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
6
5
4
0
0
0
Allow Control DIF_6 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
Allow Control DIF_5 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
Allow Control DIF_4 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
Rev 1.0,November 21, 2006
Page 4 of 13
SPECTRALINEAR [ SPECTRALINEAR INC ]
