CY28349B
Data Byte 9
Power On
Default
Bit
Pin#
Name
48MHz_DRV
Pin Description
Bit 7
–
48MHz and 24_48MHz clock output drive strength
0 = Normal
1 = High Drive
0
(Recommend to set to high drive if this output is being used
to drive both USB and SIO devices in Intel Brookdale - G
platforms)
Bit 6
Bit 5
Bit 4
–
–
–
PCI_DRV
PCI clock output drive strength
0 = Normal
1 = High Drive
0
0
0
3V66_DRV
RST_EN_WD
3V66 clock output drive strength
0 = Normal
1 = High Drive
This bit will enable the generation of a Reset pulse when a
Watchdog timer time-out occurs.
0 = Disabled
1 = Enabled
Bit 3
Bit 2
Bit 1
–
–
–
RST_EN_FC
WD_TO_STATUS
WD_EN
This bit will enable the generation of a Reset pulse after a
0
0
0
frequency change occurs.
0 = Disabled
1 = Enabled
Watchdog Timer Time-out Status bit
0 = No time-out occurs (Read); Ignore (Write)
1 = time-out occurred (Read); Clear WD_TO_STATUS
(Write)
0 = Stop and reload Watchdog Timer
1 = Enable Watchdog Timer. It will start counting down after
a frequency change occurs.
Note: CY28349B will generate system reset, reload a
recovery frequency, and lock itself into a recovery
frequency mode after a Watchdog Timer time-out occurs.
Under recovery frequency mode, CY28349B will not
respond to any attempt to change output frequency via the
SMBus control bytes. System software can unlock
CY28349B from its recovery frequency mode by clearing
the WD_EN bit.
Bit 0
–
Reserved
Reserved
0
Data Byte 10
Power On
Default
Bit
Bit 7
Pin#
Name
CPU_Skew2
Pin Description
–
–
–
CPU skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
0
0
0
Bit 6
CPU_Skew1
Bit 5
CPU_Skew0
Bit 4
–
Fixed 3V66/PCI
Fixed 3V66 and PCI output mode
0 = Disabled
1 = Enabled
0
Whenenabled, 3V66 andPCIoutputfrequencywill be fixed
at 64 MHz and 32 MHz respectively.
Rev 1.0,November 20, 2006
Page 9 of 20
SPECTRALINEAR [ SPECTRALINEAR INC ]
