CY28346
Table 4. Host Clock (HCSL) Buffer Characteristics
Characteristic
Min.
Max.
Ro
3000: (recommended)
N/A
Ros
Vout
N/A
1.2V
Table 5. CPU Clock Current Select Function
Mult0
Board Target Trace/Term Z
Reference R, Iref – Vdd (3*Rr)
Rr = 221 1%, Iref = 5.00mA
Rr = 475 1%, Iref = 2.32mA
Output Current
Ioh = 4*Iref
Voh @ Z
1.0V @ 50
0.7V @ 50
0
1
50:
50:
Ioh = 6*Iref
Table 6. Group Timing Relationship and Tolerances
Description
Offset
2.5 ns
0.0 ns
2.5 ns
Tolerance
r1.0 ns
Conditions
3V66 to PCI
3V66 Leads PCI (unbuffered mode)
0 degrees phase shift
48MUSB to 48MDOT Skew
66B(0:2) to PCI offset
r1.0 ns
r1.0 ns
66B Leads PCI (buffered mode)
USB and DOT 48M Phase Relationship
66B(0:2) to PCI Buffered Clock Skew
The 48MUSB and 48MDOT clocks are in phase. It is under-
stood that the difference in edge rate will introduce some
inherent offset. When 3V66_1/VCH clock is configured for
VCH (48-MHz) operation it is also in phase with the USB and
DOT outputs. See Figure 5.
Figure 7 shows the difference (skew) between the 3V33(0:5)
outputs when the 66M clocks are connected to 66IN. This
offset is described in the Group Timing Relationship and Toler-
ances section of this data sheet. The measurements were
taken at 1.5V.
3V66 to PCI Un-Buffered Clock Skew
66IN to 66B(0:2) Buffered Prop Delay
Figure 8 shows the timing relationship between 3V66(0:5) and
PCI(0:6) and PCI_F(0:2) when configured to run in the unbuf-
fered mode.
The 66IN to 66B(0:2) output delay is shown in Figure 6.
The Tpd is the prop delay from the input pin (66IN) to the
output pins (66B[0:2]). The outputs’ variation of Tpd is
described in the AC parameters section of this data sheet. The
measurement taken at 1.5V.
48MUSB
48MDOT
Figure 5. 48MUSB and 48MDOT Phase Relationship
66IN
Tpd
66B(0:2)
Figure 6. 66IN to 66B(0:2) Output Delay Figure
66B(0:2)
1.5-
3.5ns
PCI(0:6)
PCIF(0:2)
Figure 7. Buffer Mode – 33V66(0:1); 66BUF(0:2) Phase Relationship
Rev 1.0,November 24, 2006
Page 8 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
