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CY28341ZC-2T 参数 Datasheet PDF下载

CY28341ZC-2T图片预览
型号: CY28341ZC-2T
PDF下载: 下载PDF文件 查看货源
内容描述: 通用时钟芯片为VIA ™ P4M / KT / KM400 DDR系统 [Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems]
分类和应用: 双倍数据速率时钟
文件页数/大小: 18 页 / 228 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28341-2  
Byte 5: SDR/DDR Clock Register  
Bit @Pup Pin# Name  
Description  
7
0
45 BUF_IN threshold voltage DDR Mode, BUF_IN threshold setting. 0 = 1.15V, 1 = 1.05VSDR Mode, BUF_IN  
threshold setting. 0 = 1.35V, 1 = 1.25V  
6
5
4
3
2
1
0
1
1
1
1
1
1
1
46  
FBOUT  
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.  
29,30 DDRT/C5/SDRAM(10,11) 1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.  
31,32 DDRT/C4/SDRAM(8,9) 1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.  
35,36 DDRT/C3/SDRAM(6,7) 1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.  
37,38 DDRT/C2/SDRAM(4,5) 1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.  
41,42 DDRT/C1/SDRAM(2,3) 1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.  
43,44 DDRT/C0/SDRAM(0,1) 1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.  
Byte 6: Watchdog Register  
Bit @Pup Pin# Name  
SRESET#  
Description  
7
6
0
0
26  
1 = Pin 26 is the input pin as PD# signal. 0 = Pin 26 is the output pin as SRESET#  
signal.  
Frequency Revert This bit allows setting the Revert Frequency once the system is rebooted due to  
Watchdog time out only.0 = selects frequency of existing H/W setting1 = selects  
frequency of the second to last S/W setting. (the software setting prior to the one that  
caused a system reboot).  
5
4
0
0
WDTEST  
WD Alarm  
For IMI Test - WD-Test, ALWAYS program to '0'  
This bit is set to “1” when the Watchdog times out. It is reset to “0” when the system  
clears the WD time stamps (WD3:0).  
3
2
1
0
0
0
0
0
WD3  
WD2  
WD1  
WD0  
This bit allows the selection of the time stamp for the Watchdog timer. See Table 7  
This bit allows the selection of the time stamp for the Watchdog timer. See Table 7  
This bit allows the selection of the time stamp for the Watchdog timer. See Table 7  
This bit allows the selection of the time stamp for the Watchdog timer. See Table 7  
Table 7. Watchdog Time Stamp  
WD3  
0
WD2  
0
WD1  
0
WD0  
0
FUNCTION  
Off  
0
0
0
1
1 second  
0
0
1
0
2 seconds  
3 seconds  
4 seconds  
5 seconds  
6 seconds  
7 seconds  
8 seconds  
9 seconds  
10 seconds  
11 seconds  
12 seconds  
13 seconds  
14 seconds  
15 seconds  
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Byte 7: Dial-a-Frequency Control Register N  
Bit @Pup Pin# Name  
Description  
Rev 1.0,November 21, 2006  
Page 7 of 18