欢迎访问ic37.com |
会员登录 免费注册
发布采购

CY28341OC-2 参数 Datasheet PDF下载

CY28341OC-2图片预览
型号: CY28341OC-2
PDF下载: 下载PDF文件 查看货源
内容描述: 通用时钟芯片为VIA ™ P4M / KT / KM400 DDR系统 [Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems]
分类和应用: 晶体外围集成电路光电二极管双倍数据速率时钟
文件页数/大小: 18 页 / 228 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
 浏览型号CY28341OC-2的Datasheet PDF文件第1页浏览型号CY28341OC-2的Datasheet PDF文件第2页浏览型号CY28341OC-2的Datasheet PDF文件第3页浏览型号CY28341OC-2的Datasheet PDF文件第5页浏览型号CY28341OC-2的Datasheet PDF文件第6页浏览型号CY28341OC-2的Datasheet PDF文件第7页浏览型号CY28341OC-2的Datasheet PDF文件第8页浏览型号CY28341OC-2的Datasheet PDF文件第9页  
CY28341-2  
Data Protocol  
Power Management Functions  
The clock driver serial protocol accepts byte write, byte read,  
block write, and block read operation from the controller. For  
block write/read operation, the bytes must be accessed in  
sequential order from lowest to highest byte (most significant  
bit first) with the ability to stop after any complete byte has  
been transferred. For byte write and byte read operations, the  
system controller can access individual indexed bytes. The  
offset of the indexed byte is encoded in the command code,  
as described in Table 2.  
All clocks can be individually enabled or stopped via the  
two-wire control interface. All clocks are stopped in the low  
state. All clocks maintain a valid high period on transitions from  
running to stop and on transitions from stopped to running  
when the chip was not powered down. On power up, the VCOs  
will stabilize to the correct pulse widths within about 0.5 ms.  
Serial Data Interface  
To enhance the flexibility and function of the clock synthesizer,  
a two-signal serial interface is provided. Through the Serial  
Data Interface, various device functions such as individual  
clock output buffers, etc., can be individually enabled or  
disabled.  
The block write and block read protocol is outlined in Table 3  
while Table 4 outlines the corresponding byte write and byte  
read protocol.The slave receiver address is 11010010 (D2h).  
Table 2. Command Code Definition  
The registers associated with the Serial Data Interface  
initializes to their default setting upon power-up, and therefore  
use of this interface is optional. Clock device register changes  
are normally made upon system initialization, if any are  
required. The interface can also be used during system  
operation for power management functions.  
Bit  
Description  
7
0 = Block read or block write operation.  
1 = Byte read or byte write operation  
(6:0)  
Byte offset for byte read or byte write operation.  
For block read or block write operations, these bits  
should be ‘0000000’  
Table 3. Block Read and Block Write Protocol  
Block Write Protocol  
Block Read Protocol  
Description  
Bit  
1
Description  
Bit  
Start  
1
2:8  
9
Start  
2:8  
9
Slave address – 7 bits  
Write  
Slave address – 7 bits  
Write  
10  
Acknowledge from slave  
10  
Acknowledge from slave  
11:18  
Command Code – 8-bit ‘00000000’ stands for  
block operation  
11:18  
Command Code – 8-bit ‘00000000’ stands for  
block operation  
19  
Acknowledge from slave  
19  
20  
Acknowledge from slave  
Repeat start  
20:27 Byte Count – 8 bits  
28 Acknowledge from slave  
29:36 Data byte 0 – 8 bits  
37 Acknowledge from slave  
38:45 Data byte 1 – 8 bits  
21:27  
28  
Slave address – 7 bits  
Read  
29  
Acknowledge from slave  
Byte count from slave – 8 bits  
Acknowledge  
30:37  
38  
46  
....  
....  
....  
....  
Acknowledge from slave  
Data Byte N/Slave Acknowledge...  
Data Byte N – 8 bits  
Acknowledge from slave  
Stop  
39:46  
47  
Data byte from slave – 8 bits  
Acknowledge  
48:55  
56  
Data byte from slave – 8 bits  
Acknowledge  
....  
Data bytes from slave/Acknowledge  
Data byte N from slave – 8 bits  
Not Acknowledge  
....  
....  
....  
Stop  
Rev 1.0,November 21, 2006  
Page 4 of 18