CY28329
Pin Description
Name
Pins
Description
REF
56
3.3V 14.318 MHz clock output
14.318 MHz crystal input
XTAL_IN
XTAL_OUT
2
3
14.318 MHz crystal input
CPU, CPU [0:3]# 44, 45, 48, 49,
51, 52, 53, 54
Differential CPU clock outputs
3V66_0
33
3.3V 66 MHz clock output
3V66_1/VCH
66IN/3V66_5
35
3.3V selectable through SMBus to be 66 MHz or 48 MHz
24
66 MHz input to buffered 66BUFF and PCI or 66 MHz clock from internal VCO
66 MHz buffered outputs from 66Input or 66 MHz clocks from internal VCO
66BUFF [0:2]
/3V66 [2:4]
21, 22, 23
PCI_F [0:2]
PCI [0:6]
5, 6, 7,
33 MHz clocks divided down from 66Input or divided down from 3V66
10,11,12,13,16, PCI clock outputs divided down from 66Input or divided down from 3V66
17, 18
USB
DOT
S2
39
38
40
55
42
Fixed 48 MHz clock output
Fixed 48 MHz clock output
Special 3.3V 3-level input for Mode selection
3.3V LVTTL inputs for CPU frequency selection
S1
IREF
A precision resistor is attached to this pin which is connected to the internal current
reference
MULT0
PD#
43
25
3.3V LVTTL input for selecting the current multiplier for the CPU outputs
3.3V LVTTL input for Power_Down# (active LOW). Do not add any decoupling capac-
itors. Use an external 1.0-K: pull-up resistor.
PCI_STOP#
34
28
3.3V LVTTL input for PCI_STOP# (active LOW)
VTTPWRGD#
3.3V LVTTL input is a level-sensitive strobe used to determine when S[1:2] and
MULT0 inputs are valid and OK to be sampled (Active LOW). Once VTTPWRGD# is
sampled LOW, the status of this output will be ignored.
SDATA
SCLK
29
30
SMBus-compatible SDATA
SMBus-compatible Sclk
VDD_REF,
VDD_PCI,
1, 8, 14, 19, 32, 3.3V power supply for outputs
37, 46, 50
VDD_3V66,
VDD_48 MHz,
VDD_CPU
VDD_CORE
26
3.3V power supply for PLL
GND_REF,
GND_PCI,
GND_3V66,
GND_IREF,
VDD_CPU
4, 9, 15, 20, 31, Ground for outputs
36, 41, 47
GND_CORE
27
Ground for PLL
Rev 1.0,November 24, 2006
Page 2 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
