CY28329
Function Table[1]
66BUFF[0:2]/
3V66[2:4]
(MHz)
CPU
(MHz)
3V66[0:1](
MHz)
66IN/3V66_5
(MHz)
PCI_F/PCI
(MHz)
USB/DOT
(MHz)
S2 S1
REF0(MHz)
Notes
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
5, 6
1
1
0
0
0
1
0
1
100 MHz 66 MHz
133 MHz 66 MHz
100 MHz 66 MHz
133 MHz 66 MHz
66IN
66-MHz Input
66-MHz Input
66-MHz Input
66-MHz Input
Hi-Z
66IN/2
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
66IN
66IN/2
33 MHz
33 MHz
Hi-Z
66 MHz
66 MHz
Hi-Z
Mid
Mid
0
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
TCLK/2
TCLK/4
TCLK/4
TCLK/4
TCLK/8
TCLK
TCLK/2
1, 6
Swing Select Functions
Board Target
Trace/Term Z
Reference R, IREF =
VDD/(3*Rr)
Output
Current
Mult0
VOH @ Z,
0
50 ohm
Rr = 221 1%,
IREF = 5.00 mA
I
OH = 4*Iref
OH = 6*Iref
1.0V @ 50
1
50 ohm
Rr = 475 1%,
IREF = 2.32 mA
I
0.7V @ 50
Clock Driver Impedances
Impedance
Min.
(Ohm)
Typ.
(Ohm)
Max.
(Ohm)
Buffer Name
CPU, CPU#
VDD Range
Buffer Type
Type X1
Type 3
50
40
30
30
30
REF
3.135–3.465
3.135–3.465
3.135–3.465
3.135–3.465
20
12
12
12
60
55
55
55
PCI, 3V66, 66BUFF
Type 5
USB
DOT
Type 3A
Type 3B
Clock Enable Configuration
PD#
PCI_STOP#
CPU
IREF*2
ON
CPU#
FLOAT
ON
3V66
66BUFF
PCI_F
LOW
ON
PCI
USB/DOT
LOW
ON
VCOS/OSC
0
1
1
X
0
1
LOW
ON
LOW
ON
LOW
OFF
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
Notes:
1. TCLK is a test clock driven in on the XTALIN input in test mode.
2. “Normal” mode of operation.
3. Range of reference frequency allowed is min. = 14.316 nominal = 14.31818 MHz, max. = 14.32 MHz.
4. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
5. Required for board level “bed of nails” testing.
6. Mid is defined a Voltage level between 1.0V and 1.8V for 3 level input functionality. Low is below 0.8V. High is above 2.0V.
Rev 1.0,November 24, 2006
Page 3 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
