CY28325-3
Data Byte 3
Power-on
Default
Bit
Pin#
Name
Pin Description
6
8
SEL_48MHZ
0 = 24 MHz
1 = 48 MHz
0
5
4
3
2
1
0
7
48MHz
24_48MHz
PCI_F
1 = Enabled, 0 = Disabled
1 = Enabled, 0 = Disabled
1 = Enabled, 0 = Disabled
1 = Enabled, 0 = Disabled
1 = Enabled, 0 = Disabled
1 = Enabled, 0 = Disabled
1
1
1
1
1
1
8
10
27
26
23
AGP2
AGP1
AGP0
Data Byte 4
Power-on
Default
Bit
7
Pin#
Name
PCI_Skew1
Pin Description
–
–
PCI skew control
0
0
00 = Normal
01 = –500 ps
10 = Reserved
11 = +500 ps
6
PCI_Skew0
5
4
3
2
1
0
–
–
–
–
–
–
WD_TIMER4
WD_TIMER3
WD_TIMER2
WD_TIMER1
WD_TIMER0
These bits store the time-out value of the Watchdog Timer. The scale
of the timer is determine by the prescaler. The timer can support a
value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If the
prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80
sec. When the Watchdog Timer reaches “0,” it will set the
1
1
1
1
1
0
WD_TO_STATUS bit and generate Reset if RST_EN_WD is enabled.
WD_PRE_SCALER 0 = 150 ms
1 = 2.5 sec
Data Byte 5
Power-on
Default
Bit
Pin#
Name
Pin Description
48-MHz clock output drive strength
0 = Normal
7
7
48MHz_DRV
1
1 = High Drive
6
8
24_48MHz_DRV
24_48 MHz clock output drive strength
0 = Normal
1 = High Drive
1
5
4
3
2
45
46
–
APCI1
(Active/Inactive)
(Active/Inactive)
1
1
0
0
APIC0
SW_MULTSEL1
SW_MULTSEL0
IREF multiplier
00 = Ioh is 4 × IREF
01 = Ioh is 5 × IREF
10 = Ioh is 6 × IREF
11 = Ioh is 7 × IREF
–
1
0
1
–
REF
(Active/Inactive)
1
0
MULTSEL_Override This bit control the selection of IREF multipler.
0 = HW control; IREF multiplier is determined by MULTSEL1 input pin
1 = SW control; IREF multiplier is determined by SW_MULTSEL[0:1]
Data Byte 6
Power-on
Default
Bit
7
Pin#
Name
Pin Description
–
–
Reserved
Reserved
Reserved
Reserved
1
1
6
Rev 1.0,November 21, 2006
Page 8 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
