CY28325-3
Data Byte 6 (continued)
Power-on
Default
Bit
5
Pin#
Name
Pin Description
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
1
1
1
1
1
4
3
2
1
0
Data Byte 7
Power-on
Default
Bit
7
Pin#
Name
Pin Description
–
–
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
1
1
1
1
1
1
1
6
5
4
3
2
1
0
Data Byte 8
Power-on
Default
Bit
7
Pin#
Name
Pin Description
–
–
–
–
–
–
–
–
Revision_ID3
Revision_ID2
Revision_ID1
Revision_ID0
Vendor_ID3
Vendor_ID2
Vendor _ID1
Vendor _ID0
Revision ID bit[3]
0
0
0
0
1
0
0
0
6
Revision ID bit[2]
Revision ID bit[1]
Revision ID bit[0]
5
4
3
Bit[3] of Cypress’s Vendor ID. This bit is Read-only.
Bit[2] of Cypress’s Vendor ID. This bit is Read-only.
Bit[1] of Cypress’s Vendor ID. This bit is Read-only.
Bit[0] of Cypress’s Vendor ID. This bit is Read-only.
2
1
0
Data Byte 9
Power-on
Default
Bit
7
Pin#
Name
Reserved
PCI_DRV
Pin Description
–
–
Reserved
0
0
6
PCI clock output drive strength
0 = Low Drive
1 = High Drive
5
4
–
–
AGP_DRV
AGP clock output drive strength
0 = Low Drive
1 = High Drive
0
RST_EN_WD This bit will enable the generation of a Reset pulse when a Watchdog timer
0
0
time-out occurs.
0 = Disabled
1 = Enabled
3
–
RST_EN_FC
This bitwill enable the generation of a Resetpulseaftera frequency change
occurs.
0 = Disabled
1 = Enabled
Rev 1.0,November 21, 2006
Page 9 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
