CY2280
Switching Characteristics[6, 7]
Parameter
Output
All
Description
Test Conditions
Min. Typ. Max. Unit
t1
t2
Output Duty Cycle[8]
t1 = t1A y t1B
45
50
55
%
CPUCLK, CPU and APIC Clock
Rising and Falling Edge
Rate
Between 0.4V and 2.0V
-1,-11S,
-21S
1.0
4.0
V/ns
APIC
t2
t2
t3
t4
PCICLK
PCI Clock Rising and
Falling Edge Rate
Between 0.4V and 2.4V
Between 0.4V and 2.4V
Between 0.4V and 2.0V
Between 2.0V and 0.4V
Measured at 1.25V
-1,-11S,
-21S
1.0
0.5
0.4
0.4
4.0
2.0
1.6
1.6
V/ns
V/ns
ns
USBCLK, USB, REF Rising and
Falling Edge Rate
REF
CPUCLK
CPU Clock Rise Time
-1,-11S,
-21S
CPUCLK
CPUCLK
CPU Clock Fall Time
CPU-CPU Clock Skew
-1,-11S,
-21S
ns
t5
t6
100 175
4.0
ps
ns
CPUCLK, CPU-PCI Clock Skew[9] Measured at 1.25V for 2.5V
PCICLK
-1,-11S,
-21S
1.5
2.0
clocks, and at 1.5V for 3.3V
clocks
t7
t8
PCICLK,
PCICLK
PCI-PCI Clock Skew
Measured at 1.5V
250
4.5
ps
ns
CPUCLK, CPU-APIC Clock
Skew[10]
Measured at 1.25V for 2.5V
clocks
-21S
APIC
t9
APIC
APIC-APIC Clock Skew Measured at 1.25V
Cycle-Cycle Clock Jitter Measured at 1.25V
100 175
200 250
ps
ps
t10
CPUCLK
-1,-11S,
-21S
t11
t12
PCICLK
Cycle-Cycle Clock Jitter Measured at 1.5V
250 500
3
ps
CPUCLK, Power-up Time
PCICLK
CPU, PCI clock stabilization from
power-up
ms
Notes:
7. All parameters specified with loaded outputs.
8. Duty cycle is measured at 1.5V when V = 3.3V. When V = 2.5V, duty cycle is measured at 1.25V.
9. PCI lags CPU for -11S and -21S options.
DD
DD
10. APIC lags CPU for -21S option.
Rev 1.0,November 25, 2006
Page 5 of 11
SPECTRALINEAR [ SPECTRALINEAR INC ]
