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CY2280 参数 Datasheet PDF下载

CY2280图片预览
型号: CY2280
PDF下载: 下载PDF文件 查看货源
内容描述: 100 MHz的Pentium㈢ II时钟合成器/驱动器,具有扩频移动或台式电脑 [100 MHz Pentium㈢ II Clock Synthesizer/Driver with Spread Spectrum for Mobile or Desktop PCs]
分类和应用: 驱动器电脑PC时钟
文件页数/大小: 11 页 / 170 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY2280  
Function Table (-11S Option)  
CPU/PCI  
Ratio  
PCICLK_F  
PCICLK  
SEL100 SEL1 SEL0  
SEL_SS[2]  
CPUCLK  
Hi-Z  
REF  
APIC  
USBCLK  
Hi-Z  
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
1
N/A  
2
Hi-Z  
Hi-Z  
Hi-Z  
N/A  
2
2
2
2
3
3
3
3
3
Reserved Reserved  
Reserved Reserved  
66.66 MHz 33.33 MHz  
66.66 MHz 33.33 MHz  
14.318 MHz 14.318 MHz  
14.318 MHz 14.318 MHz  
14.318 MHz 14.318 MHz  
14.318 MHz 14.318 MHz  
48 MHz  
48 MHz  
48 MHz  
48 MHz  
TCLK/2  
48 MHz  
48 MHz  
48 MHz  
48 MHz  
N/A  
0 (downspread)  
1 (no spread)  
N/A  
TCLK/2  
TCLK/6  
TCLK[3]  
TCLK[3]  
N/A  
Reserved Reserved  
Reserved Reserved  
14.318 MHz 14.318 MHz  
14.318 MHz 14.318 MHz  
14.318 MHz 14.318 MHz  
14.318 MHz 14.318 MHz  
N/A  
0 (downspread)  
1 (no spread)  
100 MHz  
100 MHz  
33.33 MHz  
33.33 MHz  
Function Table (-21S Option)  
CPU/PCI  
Ratio  
PCICLK_F  
PCICLK  
SEL100 SEL1 SEL0  
SEL_SS[2]  
CPUCLK  
REF  
APIC  
USBCLK  
Hi-Z  
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
1
N/A  
2
2
2
2
2
3
3
3
3
3
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
N/A  
Reserved Reserved  
Reserved Reserved  
66.66 MHz 33.33 MHz  
66.66 MHz 33.33 MHz  
14.318 MHz Reserved  
14.318 MHz Reserved  
14.318 MHz 16.67 MHz  
14.318 MHz 16.67 MHz  
48 MHz  
48 MHz  
48 MHz  
48 MHz  
TCLK/2  
48 MHz  
48 MHz  
48 MHz  
48 MHz  
N/A  
0 (downspread)  
1 (no spread)  
N/A  
TCLK/2  
TCLK/6  
TCLK[3]  
TCLK/12[3]  
N/A  
Reserved Reserved  
Reserved Reserved  
14.318 MHz Reserved  
14.318 MHz Reserved  
14.318 MHz 16.67 MHz  
14.318 MHz 16.67 MHz  
N/A  
0 (downspread)  
1 (no spread)  
100 MHz  
100 MHz  
33.33 MHz  
33.33 MHz  
Actual Clock Frequency Values  
Target Frequency Actual Frequency  
(MHz)  
Clock Output  
CPUCLK  
(MHz)  
PPM  
–195  
66.67  
100  
66.654  
99.77  
CPUCLK  
USBCLK  
–2346  
167  
48.0  
48.008  
Power Management Logic  
Other  
PCICLK_F Clocks  
CPU_STOP PCI_STOP  
PWR_DWN  
CPUCLK  
PCICLK  
Osc.  
Off  
PLLs  
Off  
X
X
0
1
0
1
0
1
1
1
1
Low  
Low  
Low  
Low  
0
0
1
Low  
Low  
Running  
Running  
Running  
Running  
Running Running Running  
Running Running Running  
Running Running Running  
Running Running Running  
Low  
Running  
Low  
Running  
Running  
1
Running  
Notes:  
2. Target frequency is modulated by percentage shown (max.) when SEL_SS = 0.  
3. TCLK supplied on the XTALIN pin in Test Mode.  
Rev 1.0,November 25, 2006  
Page 3 of 11