SNC26041
One Channel Speech Controller
5.3 RAM
SNC26041 contains (64+8) nibble RAM <(64+8) x 4-bits>. The 64 nibble RAM is only
one page. Another 8 nibbles are 8 PWMIO duty registers. In our programming
structure, user can Directly use memory related command, M0 ~ M63 in the data
transfer type instructions, to access first 64 nibbles. Another 8 nibbles, user can use
PWMxL, PWMxH related command to access when PWMIO function is disabled.
(x can be 1~4)
5.4 Power Down Mode
“End” instruction makes the IC entering into Stop Mode will stop the system clock for
power savings (<3uA @VDD=3V and <6uA @VDD=4.5V.) Any valid data transition
(LꢁH or HꢁL) occurring on any IO pin can be used to start the system clock and
return to normal operating mode.
5.5 Sampling Rate Counter
The unique sampling rate counter is designed in voice channel to be able to play
diverse voices at different sample playing rates. The playing rate can be adaptively set
up among from the wide ranges of 2.5KHz to 20KHz. This architecture yields a
high-quality voice synthesis that sounds very close to its original source when played
through the same amplifier and speaker circuitry.
5.6 I/O Ports
There is one 4-bit I/O ports P2. Any I/O can be individually programmed as either
input pull low or output. Any valid data transition (Hꢁ L or LꢁH) of P2 can reactivate
the chip when it is in power-down stage.
Port Data
PAD
Port Status
Weak
To Internal Data Bus
Read Control
I/O Port Configuration
Note:
(1) Weak N-MOS can serve as pull-low resistor.
(2) The driving/sink current of P2 is up to 8mA/16mA
6
Ver: 1.7
October 14, 2009
SONIX [ SONIX TECHNOLOGY COMPANY ]
