SNC12040
One Channel Speech Controller
5.3 RAM
SNC12040 contains 64 nibble RAM (64 x 4-bits). The 64 nibble RAM is divided into
four pages (page 0 to page 3, 16 nibble RAM on each page). In our programming
structure, users can use the instructions, PAGE n (n=0 to 3) to switch and indicate the
RAM page. Besides, users can use direct mode, M0 ~ M15 in the data transfer type
instructions, to access all 16 nibbles of each page
5.4 Power Down Mode
“End” instruction makes the IC entering into Stop Mode will stop the system clock for
power savings (<3uA @VDD=3V and <6uA @VDD=4.5V.) Any valid data transition
(LꢁH or HꢁL) occurring on any IO pin can be used to start the system clock and
return to normal operating mode.
5.5 Sampling Rate Counter
The unique sampling rate counter is designed in voice channel to be able to play
diverse voices at different sample playing rates. The playing rate can be adaptively set
up among from the wide ranges of 2.5KHz to 20KHz. This architecture yields a
high-quality voice synthesis that sounds very close to its original source when played
through the same amplifier and speaker circuitry.
5.6 I/O Ports
There are three 4-bit I/O ports P1, P2, and P3. Any I/O can be individually
programmed as either input pull low or output. Any valid data transition (HꢁL or
LꢁH) of P1, P2 and P3 can reactivate the chip when it is in power-down stage.
Port Data
PAD
Port Status
Weak
To Internal Data Bus
Read Control
I/O Port Configuration
Note:
(1) Weak N-MOS can serve as pull-low resistor.
(2) The driving/sink current of P3.3 & P3.2 is up to 8mA/16mA
5
Ver: 1.4
March 17, 2005
SONIX [ SONIX TECHNOLOGY COMPANY ]
