SL74HC595
FUNCTION TABLE
Inputs
Resulting Function
Operation
Reset Serial Shift Latch Output
Shift
Register
Contents
Latch
Register
Contents
Serial
Output
SQH
Parallel
Outputs
QA-QH
Input Clock Clock Enable
A
Reset shift register
L
X
X
L,H,
L
L
U
L
U
Shift data into shift
register
H
H
H
D
X
X
L,H,
L
L
L
D
SRA
U
U
SRG SRH
U
U
SRN SRN+1
Shift register remains
unchanged
L,H, L,H,
L,H,
U
U
U
Transfer shift register
contents to latch
register
U
SRN LRN
SRN
Latch register remains
unchanged
X
X
X
X
X
X
X
X
X
L,H,
X
L
L
*
*
*
U
**
**
*
*
*
U
Enabled
Z
Enable parallel
outputs
Force outputs into
X
H
high-impedance state
SR = shift register contents
LR = latch register contents
D = data (L,H) logic level
U = remains unchanged
X = don’ t care
Z = high impedance
* = depends on Reset and Shift Clock inputs
** = depends on Latch Clock input
PIN DESCRIPTIONS
Latch Clock - Storage Latch Clock Input. A low-to-
high transition on this input latches the shift
register data.
INPUTS:
A - Serial Data Input. The data on this pin is shifted
into the 8-bit serial shift register.
Output Enable - Active-Low Output Enable. A low
on this input allows the data from the latches to
bepresented at the outputs. A high on this input
forces the outputs (QA-QH) into the high-impedance
state. The serial output is not affected by this
control unit.
CONTROL INPUTS:
Shift Clock - Shift Register Clock Input. A low-to-
high transition on this input causes the data at the
Serial Input pin to be shifted into the 8-bit shift
register.
Reset - Active-low, Asynchronous, Shift Register
Reset Input. A low on this pin resets the shift
register portion of this device only. The 8-bit latch
is not affected.
OUTPUTS:
QA-QH - Noninverted, 3-state, latch outputs.
SQH - Voninverted, Serial Data Output. This is the
output of the eighth stage of the 8-bit shift register.
This output does not have three-state capability.
System Logic
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
