SL74HC75
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25 °C to £85°C
-55°C
£125°C
Unit
ns
tPLH, tPHL Maximum Propagation Delay, D to Q (Figures 1
and 5)
2.0
4.5
6.0
125
25
155
31
190
38
32
21
26
tPLH, tPHL Maximum Propagation Delay , D to Q
(Figures 1 and 5)
2.0
4.5
6.0
110
22
19
140
28
24
165
33
28
ns
ns
ns
ns
pF
tPLH, tPHL Maximum Propagation Delay ,Latch Enable to Q
(Figures 2 and 5)
2.0
4.5
6.0
145
29
25
180
36
31
220
44
38
tPLH, tPHL Maximum Propagation Delay ,Latch Enable to Q
(Figures 2 and 5)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 3 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
CIN
Maximum Input Capacitance
-
10
10
10
Power Dissipation Capacitance (Per Latch)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption:
35
pF
PD=CPDVCC2f+ICCVCC
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
tSU
Parameter
V
25 °C to
-55°C
£85°C
£125°C
Unit
Minimum Setup Time,
Input D to Latch Enable
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
ns
ns
ns
th
Minimum Hold Time,Latch
Enable to D (Figure 4)
2.0
4.5
6.0
25
5
5
30
6
6
40
8
7
tw
Minimum Pulse Width, Latch
Enable Input
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
(Figure 2)
tr, tf
Maximum Input Rise and Fall
Times (Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
System Logic
Semiconductor
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
