SL74HC4015
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
fmax
Parameter
V
25 °C to £85°C
-55°C
£125°C
Unit
Maximum Clock Frequency (50% Duty Cycle)
(Figure 2)
2.0
4.5
6.0
6
30
35
4.8
24
28
4
20
24
MHz
tPLH, tPHL Maximum Propagation Delay, Clock to Q (Figures
2 and 5)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
ns
ns
pF
tPHL
Maximum Propagation Delay, Reset to Q (Figures
1 and 5)
2.0
4.5
6.0
205
41
35
255
51
43
310
62
53
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 3 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
CIN
Maximum Input Capacitance
-
10
10
10
Power Dissipation Capacitance (Per Latch)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
140
pF
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
tsu
Parameter
V
25 °C to
-55°C
£85°C
£125°C
Unit
ns
Minimum Setup Time, D to Clock
(Figure 4)
2.0
4.5
6.0
50
10
9.0
65
13
11
75
15
13
th
trec
tw
Minimum Hold Time, Clock to D
(Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
ns
ns
ns
ns
Minimum Recovery Time, Reset to
Clock (Figure 1)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
Minimum Pulse Width, Reset (Figure
1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
tw
Minimum Pulse Width, Clock (Figure
4)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
System Logic
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
