SL74HC165
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
fmax
Parameter
V
25 °C to £85°C
-55°C
£125°C
Unit
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 8)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH, tPHL Maximum Propagation Delay, Clock (or Clock
Inhibit) to QH or QH (Figures 1 and 8)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
ns
ns
ns
pF
tPLH, tPHL Maximum Propagation Delay , SerialShift./.Parallel
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
Load to QH or QH
(Figures 2 and 8)
tPLH, tPHL Maximum Propagation Delay, Input H to QH or QH
(Figures 3 and 8)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 8)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
CIN
Maximum Input Capacitance
-
10
10
10
Power Dissipation Capacitance (Per Package)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption:
85
pF
PD=CPDVCC2f+ICCVCC
System Logic
Semiconductor
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
