SL386
APPLICATION INFORMATION
GAIN CONTROL
INPUT BIASING
To make the SL386 a more versatile amplifier, two
pins (1 and 8) are provided for gain control. With
pins 1 and 8 open the 1.35 KW resistor sets the gain
at 20 (26 dB). If a capacitor is put from pin 1 to 8,
bypassing the 1.35 KW resistor, the gain will go up to
200 (46 dB). If a resistor is placed in series with the
capacitor, the gain can be set to any value from 20 to
200. Gain control can also be done by capacitively
coupling a resistor (or FET) from pin 1 to ground.
Additional external components can be placed in
parallel with the internal feedback resistors to tailor
the gain and frequency response for individual
applications. For example, we can compensate poor
speaker bass response by frequency shaping the
feeback path. This is done with a series RC from pin 1
to 5 (paralleling the internal 15 KW resistor). For 6 dB
effective bass boots: R@15 KW, the lowest value for
good stable operation is R=10 KW if pin 8 is open. If
pins 1 and 8 are bypassed then R as low as 2 KW can
be used. This restriction is because the amplifier is
only compensated for closed-loop gains greater the
9.
The schematic shows that both inputs are biased to
ground with a 50 KW resistor. The base current of the
input transistors is about 250 nA, so the inputs are at
at out 12.5 mV when left open. If the dc source
resistance oriving the IL386 is higher than 250 KW it
will contribute very little additional offset (about
2.5 mV at the input, 50 mV at the output). If the dc
source resistance is less than 10 KW, then shorting
the unused input to ground will keep the offset low
(about 2.5 mV at the input, 50 mV at the output). For
dc source resistances between these values we can
eliminate excess offset by putting a resistor from the
unesed input to ground, equal in value to the dc
source resistance. Of course all affset problems are
eliminated if the input is capacitively coupled.
When using the IL386 with higher gains (by pessing
the 1.35 KW resistor between pins 1 and 8) it is
necessary to bypass the unused input, preventing
degradation of gain and possible instabilities. This is
done with a 0.1 mF capacitor or a short to ground
depending on the dc source resistance on the driven
input.
SCHEMATIC DIAGRAM
System Logic
Semiconductor
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
