time, thus preserving the relevant temporal
information of the applied signals, precisely.
This unique feature permits the SP8530 to
ideally fit applications where the information
content is carried on dual carriers, such as
in-phase and quadrature phase systems.
Further, S2ADC™ architecture permits the
sampling of such signals without the necessity
of demodulating or further conditioning of the
carrier prior to conversion, potentially saving
significant amounts of other support electronics.
It is also suited to measure instantaneous
transfer functions between input signals and
their corresponding output signal.
PIN ASSIGNMENTS
Pin 1-N.C.-No Connection
Pin 2-VIN B-Analog Input B
Pin 3-VIN A- Analog Input A
Pin 4-AGND-Analog Ground
Pin 5-VSS-Digital Ground
Pin 6-SCLK-Serial Clock Input
Pin 7-DOUT Digital Data Output
Pin 8-STATUS- High During Conversion
Pin 9-CS-Chip Select Bar Input High Deselects
chip Low Selects chip
Pin 10-SD-Shutdown Input, logic low power
up, logic high = powerdown
Pin 11-VDD Digital +5V supply
Pin 12-VDA Analog +5V supply
Pin 13-OffADJ-A External Offset Adjust A
Pin 14-OffADJ-B External Offset Adjust B
Pin 15-REFOUT-Voltage Reference Output
Pin 16-GAINADJ-External Gain Adjustment
Such measurements are commonly made in test
equipment and PIN electronics as well as in
many other systems where instantaneous cause
and effect relationships are monitored.
The SP8530 permits the user to convert each
channel and digitally subtract the result in
external logic to produce a precise digital
differential result.
N.C.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GAIN ADJUST
REF OUT
V
V
B
A
IN
The SP8530 is fabricated in Sipex' Bipolar
Enhanced CMOS Process that permits state-of-
the-art design using bipolar devices in the
analog/linear section and extremely low power
CMOS in digital/logic section.
OFFSET ADJ. B
OFFSET ADJ. A
IN
AGND
SP8530
V
V
V
SS
DA
DD
CIRCUIT OPERATION
The operating circuit in Figure 1 shows a simple
circuit required to operate the SP8530. The
conversion is controlled by the user supplied
signal Chip Select Bar (CS) which selects and
deselectsthedevice,andasystemclock(SCLK).
SCLK
D
PD
CS
OUT
STATUS
A high level applied to CS asynchronously
clears the internal logic, puts the sample & hold
(CDAC)intosamplemodeandplacestheDOUT
(Data Output) pin in a high impedance state.
FEATURES
Conversion is initiated by falling edge on CS in
slave mode at which point the selected input
voltages are held and a conversion is started. A
delay of 90ns is required between the falling
edge of CS and the first rising of SCLK.
The SP8530 is a two channel simultaneous
sampling, 12-Bit serial out data acquisition
system. Thedevicecontainsahighspeed12-bit
analog to digital converter, internal reference,
andsampleandholdcircuitryforbothchannels.
The patented, simultaneous sampling feature of
this monolithic integrated circuit, permits the
user to measure and convert the analog
information on each of two channels at the same
TM
SP8530DS/01
SP8530 S2ADC - Simultaneous Sampling Analog to Digital Converter
© Copyright 2000 Sipex Corporation
5
SIPEX [ SIPEX CORPORATION ]
