Preliminary
STK14EC8
HSB
NC
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A0
2
3
A1
A18
A17
A16
A15
4
A2
A3
5
6
A4
E
7
8
G
DQ0
DQ7
DQ6
VSS
VCC
9
DQ1
VCC
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
512K x8
DQ2
DQ3
DQ5
DQ4
VCAP
A14
W
A5
A6
A7
A13
A12
A11
A10
A8
A9
NC
NC
NC
NC
44-Pin TSOP-II
(See mechanical drawing on Page 18)
PIN DESCRIPTIONS
Pin Name
I/O
Description
A
-A
Input
I/O
Address: The 19 address inputs select one of 524,288 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
18
0
DQ -DQ
7
0
E
Input
Input
W
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
V
Power Supply
I/O
Power: 3.0V, +20%, -10%
CC
HSB
Hardware Store Busy: When low this output indicates a Store is in progress (also low during
power up while busy). When pulled low external to the chip, it will initiate a nonvolatile
STORE operation. A weak pull up resistor keeps this pin high if not connected. (Connection
Optional).
V
V
Power Supply
Autostore Capacitor: Supplies power to the nvSRAM during a power loss to store data from
SRAM to nonvolatile storage elements.
CAP
Power Supply
No Connect
Ground
SS
NC
This pin is not connected to the die. (Do not connect in design; reserved for future use)
Rev 1.0
Document Control #ML0060
April, 2007
2
Simtek Confidential
SIMTEK [ SIMTEK CORPORATION ]
