Preliminary
STK14EC8
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
STK14EC8-15
STK14EC8-25
STK14EC8-45
UNITS
PARAMETER
#1
#2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
15
25
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
RC
AA
c
c
t
t
15
25
45
AVAV
AVAV
d
d
3
Address Access Time
15
10
25
12
45
20
AVQV
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
AXQX
ELQX
EHQZ
GLQX
OE
OH
LZ
d
d
e
e
5
t
3
3
3
3
3
3
AXQX
6
7
7
7
10
10
25
15
15
45
HZ
8
0
0
0
0
0
0
OLZ
OHZ
PA
9
GHQZ
b
b
10
11
ELICCH
EHICCL
15
PS
Note c: W must be high during SRAM READ cycles.
Note d: Device is continuously selected with E and G both low
Note e: Measured ± 200mV from steady state output voltage.
Note f: HSB must remain high during READ and WRITE cycles.
c,d,f
SRAM READ CYCLE #1: Address Controlled
2
AVAV
t
ADDRESS
3
AVQV
t
5
AXQX
t
DQ (DATA OUT)
DATA VALID
c,f
SRAM READ CYCLE #2: E Controlled
2
AVAV
t
ADDRESS
1
ELQV
11
EHICCL
t
t
6
ELQX
E
t
7
EHQZ
t
G
9
4
GLQV
t
GHQZ
t
8
GLQX
t
DATA VALID
DQ (DATA OUT)
10
ELICCH
t
ACTIVE
STANDBY
I
CC
Rev 1.0
Document Control #ML0060
April, 2007
5
Simtek Confidential
SIMTEK [ SIMTEK CORPORATION ]
