Preliminary
STK14EC16
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
STK14EC16-15 STK14EC16-25 STK14EC16-45
PARAMETER
UNITS
#1
#2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
2
3
4
5
6
7
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
15
25
45
ns
ns
ns
ns
ns
ns
ELQV
ACS
RC
AA
c
c
t
t
15
25
45
AVAV
ELEH
AVQV
d
d
Address Access Time
15
10
10
25
12
12
45
20
20
AVQV
Output Enable to Data Valid
Byte Enable to Data Valid
Output Hold after Address Change
GLQV
BLQV
AXQX
ELQX
OE
d
d
t
t
t
3
3
3
3
3
3
AXQX
OH
Address Change or Chip Enable to
Output Active
LZ
ns
ns
e
8
t
t
Address Change or Chip Disable to
Output Inactive
EHQZ
HZ
7
7
10
10
15
15
9
t
t
t
t
t
t
Byte Enable to Output Active
Output Enable to Output Active
Output Disable to Output Inactive
Byte Enable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
ns
ns
ns
ns
ns
ns
BLQX
GLQX
10
11
12
13
14
t
t
0
0
0
0
0
0
OLZ
e
7
7
10
10
15
15
GHQZ
OHZ
e
BHQZ
b
b
t
t
ELICCH
EHICCL
PA
15
25
45
PS
Note c: W must be high during SRAM READ cycles.
Note d: Device is continuously selected with E and G both low, LB and UB select bytes read.
Note e: Measured ± 200mV from steady state output voltage.
Note f: HSB must remain high during READ and WRITE cycles.
c,d,f
SRAM READ CYCLE #1: Address Controlled
t
AVAV (2)
Address Valid
(3)
Address
tAVQV
Data Output
Previous Data Valid
tAXQX
Output Data Valid
(6)
c,f
SRAM READ CYCLE #2: E and G Controlled
ADDRESS
2
29
tE LE H
tEHAX
1
11
tEHI CC L
tEL Q V
6
E
tELQ X
27
7
tEHQ Z
3
tAV QV
G
9
4
tG L QV
tGH Q Z
8
tG L Q X
DQ (DATA OUT)
DATA VAL ID
10
tELI CC H
AC TIVE
STAND BY
ICC
Rev 1.1
Document Control #ML0061
Jan, 2008
6
Simtek Confidential
SIMTEK [ SIMTEK CORPORATION ]
