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STK11C48-S45 参数 Datasheet PDF下载

STK11C48-S45图片预览
型号: STK11C48-S45
PDF下载: 下载PDF文件 查看货源
内容描述: 2K ×8的nvSRAM QuantumTrap⑩ CMOS非易失性静态RAM [2K x 8 nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 10 页 / 370 K
品牌: SIMTEK [ SIMTEK CORPORATION ]
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STK11C48  
Internally, RECALL is a two-step procedure. First,  
the SRAM data is cleared, and second, the nonvola-  
tile information is transferred into the SRAM cells.  
After the tRECALL cycle time the SRAM will once again  
be ready for READ and WRITE operations. The  
RECALL operation in no way alters the data in the  
Nonvolatile Element cells. The nonvolatile data can  
be recalled an unlimited number of times.  
HARDWARE PROTECT  
The STK11C48 offers hardware protection against  
inadvertent STORE operation during low-voltage  
conditions. When VCC < VSWITCH, all software STORE  
operations are inhibited.  
LOW AVERAGE ACTIVE POWER  
The STK11C48 draws significantly less current  
when it is cycled at times longer than 50ns. Figure 2  
shows the relationship between ICC and READ cycle  
time. Worst-case current consumption is shown for  
both CMOS and TTL input levels (commercial tem-  
perature range, VCC = 5.5V, 100% duty cycle on  
chip enable). Figure 3 shows the same relationship  
for WRITE cycles. If the chip enable duty cycle is  
less than 100%, only standby current is drawn  
when the chip is disabled. The overall average cur-  
rent drawn by the STK11C48 depends on the fol-  
lowing items: 1) CMOS vs. TTL input levels; 2) the  
duty cycle of chip enable; 3) the overall cycle rate  
for accesses; 4) the ratio of READs to WRITEs; 5)  
POWER-UP RECALL  
During power up, or after any low-power condition  
(VCC < VRESET), an internal RECALL request will be  
latched. When VCC once again exceeds the sense  
voltage of VSWITCH, a RECALL cycle will automatically  
be initiated and will take tRESTORE to complete.  
If the STK11C48 is in a WRITE state at the end of  
power-up RECALL, the SRAM data will be corrupted.  
To help avoid this situation, a 10K Ohm resistor  
should be connected either between W and system  
VCC or between E and system VCC.  
the operating temperature; 6) the V level; and 7) I/  
cc  
O loading.  
100  
80  
60  
40  
20  
0
100  
80  
60  
TTL  
CMOS  
40  
TTL  
20  
CMOS  
0
50  
100  
150  
200  
50  
100  
150  
200  
Cycle Time (ns)  
Cycle Time (ns)  
Figure 2: I (max) Reads  
Figure 3: I (max) Writes  
CC  
CC  
March 2006  
8Document Control # ML0003 rev 0.2