SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.7.16 FLASH Memory Data...........................................................................................................................................80
9.7.17 EEPROM Memory Address – Command + Status ..............................................................................................81
9.7.18 EEPROM Memory Data.......................................................................................................................................81
9.7.19 FIFO Port – IDE0.................................................................................................................................................82
9.7.20 FIFO Pointers1– IDE0 .........................................................................................................................................82
9.7.21 FIFO Pointers2– IDE0 .........................................................................................................................................83
9.7.22 FIFO Port – IDE1.................................................................................................................................................83
9.7.23 FIFO Pointers1– IDE1 .........................................................................................................................................84
9.7.24 FIFO Pointers2– IDE1 .........................................................................................................................................84
9.7.25 IDE0 Task File Register 0....................................................................................................................................85
9.7.26 IDE0 Task File Register 1....................................................................................................................................85
9.7.27 IDE0 Task File Register 2....................................................................................................................................86
9.7.28 IDE0 Read Ahead Data .......................................................................................................................................86
9.7.29 IDE0 Task File Register 0 – Command Buffering ................................................................................................87
9.7.30 IDE0 Task File Register 1 – Command Buffering ................................................................................................87
9.7.31 IDE0 UDMA Control.............................................................................................................................................88
9.7.32 IDE0 Virtual DMA/PIO Read Ahead Byte Count..................................................................................................88
9.7.33 IDE0 Task File Timing + Configuration + Status..................................................................................................89
9.7.34 IDE0 PIO Timing..................................................................................................................................................90
9.7.35 IDE0 DMA Timing................................................................................................................................................91
9.7.36 IDE0 UDMA Timing .............................................................................................................................................92
9.7.37 Test Register – IDE0 ...........................................................................................................................................93
9.7.38 Data Transfer Mode – IDE0.................................................................................................................................94
9.7.39 IDE1 Task File Register 0....................................................................................................................................94
9.7.40 IDE1 Task File Register 1....................................................................................................................................95
9.7.41 IDE1 Task File Register 2....................................................................................................................................95
9.7.42 IDE1 Read/Write Ahead Data..............................................................................................................................96
9.7.43 IDE1 Task File Register 0 – Command Buffering ................................................................................................96
9.7.44 IDE1 Task File Register 1 – Command Buffering ................................................................................................97
9.7.45 Rserved Register.................................................................................................................................................97
9.7.46 IDE1 Virtual DMA/PIO Read Ahead Byte Count..................................................................................................98
9.7.47 IDE1 Task File Timing + Configuration + Status..................................................................................................98
9.7.48 IDE1 PIO Timing..................................................................................................................................................99
9.7.49 IDE1 DMA Timing..............................................................................................................................................100
9.7.50 IDE1 UDMA Timing ...........................................................................................................................................100
9.7.51 Test Register – IDE1 .........................................................................................................................................101
9.7.52 Data Transfer Mode – IDE1...............................................................................................................................102
10. Design for Testability ...................................................................................................................103
10.1 Test Mode Register.................................................................................................................................. 104
10.2 NAND Tree Test........................................................................................................................................ 104
10.3 Full Chip Internal Scan............................................................................................................................ 106
10.4 PLL TEST .................................................................................................................................................. 107
10.4.1 BYPASSING the VCO...........................................................................................................................................107
10.4.2 TESTING the VCO................................................................................................................................................107
11. Programming Sequences.............................................................................................................108
11.1 Recommended Initialization Sequence for the SiI 0680A.................................................................... 108
11.2 ATA/ATAPI Device Initialization ............................................................................................................. 108
11.3 Initialization of Controller Channel Timing Registers.......................................................................... 109
NOTE: When using PIO to perform a data transfer, this register only instructs the controller as to whether or not it should
monitor the IORDY signal when the task file data register is accessed. Any value other than 00H will cause the controller
to monitor the IORDY signal.............................................................................................................................................110
11.4 Issue ATA Command............................................................................................................................... 110
11.5 IDE PIO Mode Read/Write Operation ..................................................................................................... 110
If no error, repeat the previous four steps until all data for the write command has been transferred or an error has been
detected. ..........................................................................................................................................................................111
11.6 Watchdog Timer Operation..................................................................................................................... 111
11.7 IDE PIO Mode Read Ahead Operation ................................................................................................... 113
11.8 IDE MDMA/UDMA Read/Write Operation............................................................................................... 113
11.9 IDE Virtual DMA Read/Write Operation ................................................................................................. 114
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
5
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