Si510/511
Table 4. Output Clock Jitter and Phase Noise (LVPECL)
VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = LVPECL
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
1
Period Jitter
(RMS)
JPRMS
10k samples
—
—
1.3
ps
1
Period Jitter
(Pk-Pk)
JPPKPK
10k samples
—
—
—
11
ps
ps
Phase Jitter
(RMS)
φJ
1.875 MHz to 20 MHz integration
0.31
0.5
2
bandwidth (brickwall)
12 kHz to 20 MHz integration band-
—
0.8
1.0
ps
2
width (brickwall)
Phase Noise,
156.25 MHz
φN
100 Hz
1 kHz
—
—
—
—
—
—
—
—
—
—
–86
–109
–116
–123
–136
3.0
—
—
—
—
—
—
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
10 kHz
100 kHz
1 MHz
Additive RMS
Jitter Due to
JPSR
SPR
10 kHz sinusoidal noise
100 kHz sinusoidal noise
500 kHz sinusoidal noise
1 MHz sinusoidal noise
3.5
ps
External Power
3
Supply Noise
3.5
ps
3.5
ps
Spurious
LVPECL output, 156.25 MHz,
offset>10 kHz
–75
dBc
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
3. 156.25 MHz. Increase in jitter on output clock due to sinewave noise added to VDD (2.5/3.3 V = 100 mVPP).
6
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Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 29, 2021
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