Si500S
Condition
Min
—
—
—
—
—
—
—
—
—
—
—
—
Typ
13.9
16.7
15.8
19.3
17.7
21.5
18.1
18.0
16.8
11.8
9.7
Max
16
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Parameters
1.8 V option, 40 pF, 40 MHz, CMOS
1.8 V option, 10 pF, 200 MHz, CMOS
2.5 V option, 40 pF, 40 MHz, CMOS
2.5 V option, 10 pF, 200 MHz, CMOS
3.3 V option, 40 pF, 40 MHz, CMOS
3.3 V option, 10 pF, 200 MHz, CMOS
SSTL-3.3, 200 MHz
19
18
22
20
24
Supply Current
20.2
19.7
18.7
13.1
10.7
1.9
SSTL-2.5, 200 MHz
SSTL-1.8, 200 MHz
Output Stopped, CMOS
Tri-State
Powerdown
1.0
54 +
13 ns/TCLK
Output Symmetry
0.5 x VDD
46 – 13 ns/TCLK
—
—
%
CMOS, CL = 15 pF measured from
20 to 80% of VDD
1.4
2.0
ns
Rise and Fall Times3
SSTL
—
VDD – 0.5
—
—
—
—
—
—
—
—
—
—
0.6
ns
V
VOH, sourcing 9 mA
—
0.5
CMOS Output Voltage
V
OL, sinking 9 mA
V
VOH
VOL
VOH
VOL
VOH
VOL
VTT + 0.375
—
—
SSTL-1.8 Output Voltage4
SSTL-2.5 Output Voltage4
SSTL-3.3 Output Voltage5
V
V
V
VTT – 0.375
—
VTT + 0.48
—
VTT – 0.48
—
VTT + 0.48
—
VTT – 0.48
From time VDD crosses min spec
supply
Powerup Time
—
—
—
—
—
—
2
ms
ns
ns
250 +
3 x TCLK
OE Deassertion to Clk Stop
Return from Output Driver
Stopped Mode
250 +
3 x TCLK
Return from Tri-State Time
—
—
—
—
12 + 3 x TCLK
2
µs
Return from Powerdown Time
ms
ps
RMS
Period Jitter (1-sigma)
SSTL3
—
1
2
1 MHz – 0.4 x FOUT, SSTL or CMOS
and CL < 7 pF,
ps
RMS
Integrated Phase Jitter
—
0.7
1.5
FOUT > 2.5 MHz
Notes:
1. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4. VTT = .5 x VDD
.
5. VTT = .45 x VDD
.
2
Rev. 1.1
SILICON [ SILICON ]
