Si500D
Parameters
Condition
Min
Typ
Max
Units
Return From Powerdown Time
—
—
2
ms
ps
RMS
Non-CMOS
—
—
—
—
1
2
3
Period Jitter (1-sigma)
ps
RMS
CMOS, C = 7 pF
1
L
1.0 MHz – min(20 MHz,
ps
RMS
0.6
0.7
1
0.4 x F
),non-CMOS
OUT
Integrated Phase Jitter
1.0 MHz – min(20 MHz,
0.4 x F ),CMOS format
ps
RMS
1.5
OUT
Notes:
1. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4. VTT = .5 x VDD
.
5. VTT = .45 x VDD
.
Rev. 1.1
3
SILICON [ SILICON ]
