APPLICATION NOTES
MANUAL RESET
RESET OUTPUT
The SGM811/SGM812 is equipped with a manual reset input
This input is designed to operate in a noisy environment
where unwanted glitches could be induced. These glitches
could be produced by the bouncing action of a switch contact,
or where a manual reset switch may be located some distance
away from the circuit (the cabling of which may pick-up
noise).
The manual reset input is guaranteed to ignore logically valid
inputs that are faster than 100 ns and to accept inputs longer in
duration than 10 µs.
On power-up and after VCC rises above the reset threshold, an
internal timer holds the reset output active for 240 ms (typical).
This is intended as a power-on reset signal for the processor. It
allows time for both the power supply and the microprocessor
to stabilize after power-up. If a power supply brownout or
interruption occurs, the reset output is similarly activated and
remains active for 240 ms (typical) after the supply recovers.
This allows time for the power supply and microprocessor to
stabilize.
The SGM811 provides an active low reset output (
while the SGM812 provides an active high output (
During power-down of the SGM811, the
)
).
RESET
RESET
BENEFITS OF A VERY ACCURATE RESET THRESHOLD
output
RESET
remains valid (low) with VCC as low as 1 V. This ensures that
the microprocessor is held in a stable shutdown condition as
the supply falls and also ensures that no spurious activity can
occur via the microprocessor as it powers up.
Because the SGM811/SGM812 can operate effectively even
when there are large degradations of the supply voltages, the
possibility of a malfunction during a power failure is greatly
reduced. Another advantage of the SGM811/SGM812 is its
very accurate internal voltage reference circuit. Combined,
Glitch Immunity
these
benefits
produce
an
exceptionally
reliable
microprocessor supervisory circuit.
The SGM811/SGM812 contains internal filtering circuitry
providing glitch immunity from fast transient glitches on the
power supply line.
VCC
VCC
VREF
SGM811
VCC
VREF
VREF
VREF
RESET
RESET
t1
t1
GND
t1=
Time = 240ms Typical
RESET
VREF =
Voltage Threshold
RESET
Figure 1. Ensuring a Valid
Output Down to VCC = 0V
RESET
Figure 2. Power Fail
Timing
RESET
ENSURING A VALID RESET OUTPUT DOWN TO VCC = 0 V
When VCC falls below1.0 V, the SGM811/SGM812’s no
INTERFACING TO OTHER DEVICES
Output
RESET
longer sinks current. Therefore, a high impedance CMOS logic
input connected to may drift to undetermined logic
The SGM811/SGM812 is designed to integrate with as many
devices as possible. One feature of the SGM811/SGM812 is the
reset output, which is directly proportional to VCC (this is
guaranteed only while VCC is greater than 1 V). This enables
the part to be used with both 3 V and 5 V, or any nominal
voltage within the minimum and maximum specifications for
VCC.
RESET
levels. To eliminate this problem, a 100 kΩ resistor should be
connected from to ground.
RESET
７
SGM811/812
SGMICRO [ Shengbang Microelectronics Co, Ltd ]
