Power-Supply Bypassing and Layout
APPLICATION NOTES
Driving Capacitive Loads
The SGM2358 operates from either a single +3V to +5.5V
supply or dual ±1.5V to ±2.75V supplies. For single-supply
operation, bypass the power supply VDD with a 0.1µF ceramic
capacitor which should be placed close to the VDD pin. For
dual-supply operation, both the VDD and the VSS supplies should
be bypassed to ground with separate 0.1µF ceramic capacitors.
The SGM2358 can directly drive 250pF in unity-gain without
oscillation. The unity-gain follower (buffer) is the most sensitive
configuration to capacitive loading. Direct capacitive loading
reduces the phase margin of amplifiers and this results in ringing
or even oscillation. Applications that require greater capacitive
drive capability should use an isolation resistor between the
output and the capacitive load like the circuit in Figure 1. The
isolation resistor RISO and the load capacitor CL form a zero to
increase stability. The bigger the RISO resistor value, the more
stable VOUT will be. Note that this method results in a loss of gain
2.2µF tantalum capacitor can be added for better performance.
VDD
10µF
VDD
10µF
0.1µF
accuracy because RISO forms a voltage divider with the RLOAD
.
0.1µF
Vn
Vp
RISO
VOUT
Vn
Vp
½ SGM2358
VOUT
½ SGM2358
VOUT
VIN
½ SGM2358
CL
10µF
Figure 1. Indirectly Driving Heavy Capacitive Load
0.1µF
An improvement circuit is shown in Figure 2, It provides DC
accuracy as well as AC stability. RF provides the DC accuracy by
connecting the inverting signal with the output, CF and RIso serve
to counteract the loss of phase margin by feeding the high
frequency component of the output signal back to the amplifier’s
inverting input, thereby preserving phase margin in the overall
feedback loop.
VSS(GND)
VSS
Figure 3. Amplifier with Bypass Capacitors
CF
RF
RISO
½ SGM2358
VOUT
VIN
CL
RL
Figure 2. Indirectly Driving Heavy Capacitive Load with DC
Accuracy
For no-buffer configuration, there are two others ways to
increase the phase margin: (a) by increasing the amplifier’s gain
or (b) by placing a capacitor in parallel with the feedback resistor
to counteract the parasitic capacitance associated with inverting
node.
7
SGM2358