E0C88409
■ PIN CONFIGURATION
• Pin layout for expanded 4M mode
(for multi-chip system)
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
OSC1
OSC2
VD1
OSC3
OSC4
VDD
LCDEN
DOFF
YD
FR
XSCL
LP
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
N.C.
N.C.
AGND
AVREF
E0C88409
A19
A20
A21
RD
WR
INDEX
CE0
(CE1) R31
(CE2) R32
(TOUT0/FOUT3) R40
■ PIN DESCRIPTION
Pin name
Pin No.
44
50
47
24
I/O
–
–
O
–
–
Function
VDD
VSS
VD1
Power supply (+) pin
Power supply (GND) pin
Voltage regulator output pin
AVDD
AGND
Power supply (+) pin for analog circuit system
GND pin for analog circuit system
27
AVSS
AVREF
25
26
–
I
Power supply (GND) pin for analog circuit system
Reference voltage input pin for analog circuit system
OSC1
OSC2
OSC3
OSC4
MCU/MPU
K00~K07
K10 (EXCL00)
K11 (EXCL01)
K12~K13
A00~A21
RD
49
48
46
45
51
52~59
60
I
O
I
O
I
I
I
I
I
OSC1 oscillation input pin (32 kHz crystal, CR oscillation, external clock input)
OSC1 oscillation output pin
OSC3 oscillation input pin (crystal/ceramic, CR oscillation, external clock input)
OSC3 oscillation output pin
MCU/MPU mode stting pin
Input port pin
Input port pin or external clock input pin for event counter (Timer 0)
Input port pin or external clock input pin for event counter (Timer 1)
Input port pin
Address bus
Read signal output pin
61
62~63
73~94
95
96
97
98
99
100
1
2
65~72
3
4
5
6
7
8
9
10
11
12
13
14
23~18
17,16
43
42
41
40
39
38
37~30
64
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
I
WR
CE0
Write signal output pin
Chip enable signal output pin
CE1 (R31)
CE2 (R32)
R40 (TOUT0/FOUT3)
R41 (TOUT1/FOUT1)
R42 (BZ)
Chip enable signal output pin or output port pin
Chip enable signal output pin or output port pin
Output port pin or TOUT0/FOUT3 clock output pin
Output port pin or TOUT1/FOUT1 clock output pin
Output port pin or buzzer signal output pin
Data bus
D0~D7
P10 (SIN)
I/O port pin or serial I/F data input pin
I/O port pin or serial I/F data output pin
P11 (SOUT)
P12 (SCLK)
P13 (SRDY)
P14 (SIN/IRI)
P15 (SOUT/IRO)
P16 (SCLK)
P17 (SRDY)
P20 (BYH)
P21 (BYL)
P22 (BXH)
P23 (BXL)
P30~P35 (AD0~AD5)
P36, P37 (AD6/DA0, AD7/DA1)
LCDEN
DOFF
YD
FR
XSCL
LP
SD0~SD7
RESET
TEST
I/O port pin or serial I/F clock input/output pin
I/O port pin or serial I/F ready signal output pin
I/O port pin, serial I/F data input or IR receiver input pin
I/O port pin, serial I/F data output or IR transmitter output pin
I/O port pin or serial I/F clock input/output pin
I/O port pin or serial I/F ready signal output pin
I/O port pin or touch panel controller BYH signal output pin
I/O port pin or touch panel controller BYL signal output pin
I/O port pin or touch panel controller BXH signal output pin
I/O port pin or touch panel controller BXL signal output pin
I/O port pin or A/D converter analog signal input pin
I/O port pin, A/D converter analog signal input pin or D/A converter analog signal output pin
LCD controller enable signal output pin
LCD controller forced blank signal output pin
LCD controller scan start pulse output pin
LCD controller frame signal output pin
LCD controller shift clock output pin
LCD controller latch pulse output pin
LCD controller data output pin
Initial reset input pin
1
15
I
Test input pin
1 TEST is the terminal used for factory inspection of the IC. For normal operation, be sure to connect the TEST terminal to VDD.
(Note) The pin configuration is different from that of single-chip mode or expanded 64K mode. Please refer to the technical manual before
designing the system.
3
SEIKO [ SEIKO EPSON CORPORATION ]
