E0C88308
● SVD Circuit
(Unless otherwise specified: VDD = 1.8 to 5.5V, VSS = 0V, Ta = 25°C)
Characteristic
Symbol
Condition
SVD Level 1 → Level 0
Level 2 → Level 1
Min.
Typ.
1.82
2.00
2.18
2.36
Max.
Unit Note
SVD voltage
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Level 3 → Level 2
Level 4 → Level 3
Level 5 → Level 4
Level 6 → Level 5
Level 7 → Level 6
Level 8 → Level 7
Level 9 → Level 8
Level 10 → Level 9
Level 11 → Level 10
Level 12 → Level 11
Level 13 → Level 12
Level 14 → Level 13
Level 15 → Level 14
Typ×0.92 2.54 Typ×1.08
2.72
2.90
3.08
3.26
3.45
3.65
3.85
4.05
4.25
4.50
Typ×0.88
Typ×1.12
● Analog Comparator
(Unless otherwise specified: VDD = 1.8 to 5.5V, VSS = 0V, Ta = 25°C)
Characteristic
Symbol
Condition
Min.
0.7
0.7
Typ.
Max.
DD - 0.7
DD - 0.7
20
Unit Note
Analog comparator
operating voltage input range
Analog comparator offset voltage
V
V
V
CMIP Non-inverted input (CMPP)
CMIM Inverted input (CMPM)
V
V
V
V
9
9
9
CMOF
V
V
CMIP = 0.7V to VDD - 0.7V
CMIM = 0.7V to VDD - 0.7V
mV
Analog comparator stability time
Analog comparator response time
t
t
CMP1
CMP2
1
2
mS
mS
10
9
11
VCMIP = 0.7V to VDD - 0.7V
VCMIM = 0.7V to VDD - 0.7V
VCMIP = VCMIM ± 0.025V
Note) 9 When "without pull-up resistor" (comparator input terminal) is selected by mask option.
10 Stability time is the time from turning the circuit ON until the circuit is stabilized.
11 Response time is the time that the output result responds to the input signal.
● Current Consumption
(Unless otherwise specified: VDD = Within the operating voltage in each operating mode, VSS = 0V, Ta = 25°C,
OSC1 = 32.768kHz crystal oscillation,
CG = 25pF, OSC3 = External clock input, Non heavy load protection mode, C1–C9 = 0.1µF, No panel load)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit Note
1
2
3
4
Power current
(Normal mode)
I
DD1
DD2
DD3
DD4
HVL
DD1
DD2
DD3
HVL
DD1
DD2
DD3
DD4
HVL
LCDN
In SLEEP status
In HALT status
CPU is in operating (32.768kHz)
CPU is in operating (1MHz)
In heavy load protection mode
In SLEEP status
0.3
2
1
5
18
0.60
50
1
µA
µA
µA
mA
*
*
*
*
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
14
0.45
25
0.2
1
8
15
1
µA
µA
µA
µA
µA
µA
µA
µA
mA
µA
µA
µA
µA
µA
µA
µA
µA
12
12
1
2
3
Power current
(Low power mode)
*
*
*
In HALT status
5
CPU is in operating (32.768kHz)
In heavy load protection mode
In SLEEP status
12
30
3
10
30
1.00
70
5
30
60
75
100
10
50
1
2
3
4
Power current
(High speed mode)
*
*
*
*
In HALT status
5
CPU is in operating (32.768kHz)
CPU is in operating (1MHz)
In heavy load protection mode
24
0.70
35
2.5
15
30
25
40
4
12
LCD drive circuit current
SVD circuit current
LCDH In heavy load protection mode
DD = 3.0V
12
13
12
SVDN
V
SVDH In heavy load protection mode
CMP1 CMPXDT = "1"
CMP2 CMPXDT = "0"
Analog comparator circuit current
OSC1 CR oscillation current
CR1
20
14
1
2
3
4
OSC1: Stop,
OSC1: Oscillating, OSC3: Stop,
OSC1: Oscillating, OSC3: Stop,
OSC3: Stop,
CPU, ROM, RAM: SLEEP status,
CPU, ROM, RAM: HALT status,
CPU, ROM, RAM: Operating in 32.768kHz, Clock timer: Operating, Others: Stop status
Clock timer: Operating, Others: Stop status
Clock timer: Stop,
Clock timer: Operating, Others: Stop status
Others: Stop status
OSC1: Oscillating, OSC3: Oscillating, CPU, ROM, RAM: Operating in 1MHz,
12 It is the value of current which flows in the heavy load protection circuit when in the heavy load protection mode (OSC3 ON or buzzer ON).
Note)
13 The value in x V can be found by the following expression:
I
SVDN (VDD = x V) = (x × 20) - 30 (Typ. value), ISVDN (VDD = x V) = (x × 30) - 30 (Max. value
)
14 When OSC1 CR oscillation circuit is selected by the mask option.
6
SEIKO [ SEIKO EPSON CORPORATION ]
