E0C6S46
■ PIN CONFIGURATION
No. Pin name No. Pin name No. Pin name No. Pin name
QFP5-128pin
1
2
3
4
5
6
7
8
9
V
V
V
L3
L4
L5
33 SEG33
34 N.C.
65 SEG2
66 SEG1
67 SEG0
68 SCLK
69 N.C.
70 SOUT
71 SIN
72 K13
73 K12
74 K11
75 K10
76 K03
77 K02
78 K01
79 K00
80 P33
81 P32
82 P31
83 P30
84 P23
85 P22
86 P21
87 P20
88 P13
89 P12
90 P11
91 P10
92 P03
93 P02
94 P01
95 P00
96 R43
97 R42
98 N.C.
99 R41
102
65
35 SEG32
36 SEG31
37 SEG30
38 SEG29
39 SEG28
40 SEG27
41 SEG26
42 SEG25
43 SEG24
44 SEG23
45 SEG22
46 SEG21
47 SEG20
48 SEG19
49 SEG18
50 SEG17
51 SEG16
52 SEG15
53 SEG14
54 SEG13
55 SEG12
56 SEG11
57 SEG10
58 SEG9
59 SEG8
60 SEG7
61 SEG6
62 SEG5
63 SEG4
64 SEG3
CF
100 R40
101 R33
102 R32
103 R31
104 R30
105 R23
106 R22
107 R21
108 R20
109 R13
110 R12
111 R11
112 R10
113 R03
114 R02
115 R01
116 R00
117 VSS
118 RESET
119 TEST
120 OSC4
121 OSC3
122 VS1
N.C.
CE
CD
CC
CB
103
64
10 CA
11 COM0
12 COM1
13 COM2
14 COM3
15 COM4
16 COM5
17 COM6
18 COM7
19 COM8
20 COM9
21 COM10
22 COM11
23 COM12
24 COM13
25 COM14
26 COM15
27 SEG39
28 SEG38
29 SEG37
30 SEG36
31 SEG35
32 SEG34
E0C6S46
INDEX
39
128
1
38
123 OSC2
124 OSC1
125 VDD
126 VREF
127 VL1
128 VL2
N.C. = No Connection
■ PIN DESCRIPTION
Pin name
Pin No.
125
117
I/O
–
–
Function
V
V
V
V
DD
SS
S1
Power supply (+)
Power supply (-)
122
127, 128, 1–3
–
–
Internal logic system/oscillation system regulated voltage output
L1–VL5
LCD system power supply
1/4 bias generated internally, 1/5 bias generated externally
LCD system power test pin
1
2
V
REF
126
10–6, 4
124
O
–
I
CA–CF
OSC1
LCD system voltage booster condenser connecting pin
Crystal oscillator input
OSC2
OSC3
OSC4
123
121
120
O
I
O
Crystal oscillator output, C
CR or ceramic oscillator input
CR or ceramic oscillator output
D
buiil-in
1
1
COM0–COM15
SEG0–SEG39
K00–K03
K10–K13
P00–P03
P10–P13
P20–P23
P30–P33
R00–R03
R10–R13
R20–R23
R30–R32
R33
R40
R41
R42
R43
SIN
SOUT
11–26
67–35, 33–27
79–76
75–72
95–92
91–88
87–84
83–80
116–113
112–109
108–105
104–102
101
O
O
I
I
LCD common output (1/8 duty or 1/16 duty is selected on software)
LCD segment output
Input port (pull up resistor is available by mask option)
Input port (pull up resistor is available by mask option)
1
1
I/O I/O port
I/O I/O port
I/O I/O port
I/O I/O port or output port
Complementary output or
Nch open drain output
1
1
O
O
O
O
O
O
O
O
O
I
Output port
Output port
Output port
Output port
Output port, SRDY output or PTCLK output
Output port or FOUT output
1
1
100
99
97
96
71
70
Output port
Output port, BZ output or FOUT output
Output port or BZ output
1
1
Serial interface data input
Serial interface data output
O
SCLK
68
I/O Serial interface clock input/output
RESET
TEST
118
119
I
I
Initial reset input terminal
Testing input terminal
3
1 Selected by mask option
2 Leave the VREF pin unconnected (N.C.).
3 The TEST pin is used when the IC load is being detected. During ordinary operation be certain to connect this pin to VDD
.
3
SEIKO [ SEIKO EPSON CORPORATION ]
