E0C63557
<Master mode>
VOH
SCLK OUT
SOUT
VOL
tsmd
VOH
VOL
tsms
tsmh
VIH1
VIL1
SIN
<Slave mode>
VIH1
SCLK IN
SOUT
SIN
VIL1
tssd
VOH
VOL
tsss
tssh
VIH1
VIL1
Asynchronous System
(Condition: VDD=2.2 to 5.5V, VSS=0V, Ta=-20 to 70°C)
Characteristic
Start bit detection error time
Erroneous start bit detection range time
1: Start bit detection error time is a logical delay time from inputting the start bit until internal sampling begins operating.
(Time as far as AC is excluded.)
Symbol
tsa1
tsa2
Min.
0
9t/16
Typ.
Max.
t/16
10t/16
Unit
S
S
1
2
2: Erroneous start bit detection range time is a logical range to detect whether a LOW level (start bit) has been input again
after a start bit has been detected and the internal sampling clock has started. When a HIGH level is detected, the start bit detection
circuit is reset and goes into a wait status until the next start bit. (Time as far as AC is excluded.)
Start bit
Stop bit
SIN
tsa1
Sampling
clock
t
Erroneous
start bit
detection signal
tsa2
● Timing Chart
System clock switching
OSCC
5 msec min.
1 instruction execution
time or longer
CLKCHG
8
SEIKO [ SEIKO EPSON CORPORATION ]
