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E0C6282D 参数 Datasheet PDF下载

E0C6282D图片预览
型号: E0C6282D
PDF下载: 下载PDF文件 查看货源
内容描述: [4-BIT, MROM, 0.032768MHz, MICROCONTROLLER, UUC, DIE]
分类和应用: 时钟外围集成电路
文件页数/大小: 9 页 / 102 K
品牌: SEIKO [ SEIKO EPSON CORPORATION ]
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E0C6282  
Analog Circuit Characteristics and Current Consumption  
E0C6282 (Normal Operating Mode)  
(Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25°C, C  
G
=25pF, VS1/VL1–VL4 are internal voltage, C1–C6=0.1µF)  
Characteristic  
Internal voltage  
Symbol  
Condition  
Min.  
0.5•VL2  
-0.1  
Typ.  
Max.  
0.5•VL2  
+0.1  
Unit  
V
V
V
V
V
V
L1  
Connect 1Mload resistor between VDD and VL1  
(without panel load)  
Connect 1Mload resistor between VDD and VL2  
(without panel load)  
Connect 1Mload resistor between VDD and VL3  
(without panel load)  
Connect 1Mload resistor between VDD and VL4  
(without panel load)  
L2  
-2.25  
-2.10  
-1.95  
V
V
V
L3  
3•VL1  
-0.1  
4•VL1  
-0.1  
3•VL1  
×0.9  
4•VL1  
×0.9  
-2.25  
100  
L4  
SVD voltage  
SVD  
-2.55  
-2.40  
V
µS  
V
SVD circuit response time  
Analog comparator  
input voltage  
Analog comparator  
offset voltage  
t
SVD  
V
V
V
IP  
Noninverted input (CMPP)  
Inverted input (CMPM)  
V
SS+0.3  
V
DD-0.9  
IM  
OF  
10  
mV  
mS  
Analog comparator  
response time  
t
CMP  
V
IP=-1.5V, VIM=VIP±15mV  
1
Current consumption  
I
I
OP1  
OP2  
During HALT *1  
During operation *1  
During HALT *1  
Without panel load  
OSC1 is crystal oscillation  
Without panel load  
1.5  
4.0  
6.0  
8.7  
3.0  
7.0  
10.5  
14.0  
µA  
µA  
µA  
µA  
During operation *1  
OSC1 is CR oscillation  
1: The SVD circuit and analog voltage comparator are turned OFF.  
E0C6282 (Heavy Load Protection Mode)  
(Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL4 are internal voltage, C1–C6=0.1µF)  
Characteristic  
Internal voltage  
Symbol  
Condition  
Min.  
0.5•VL2  
-0.1  
Typ.  
Max.  
0.5•VL2  
+0.1  
Unit  
V
V
V
V
V
V
L1  
Connect 1Mload resistor between VDD and VL1  
(without panel load)  
Connect 1Mload resistor between VDD and VL2  
(without panel load)  
Connect 1Mload resistor between VDD and VL3  
(without panel load)  
Connect 1Mload resistor between VDD and VL4  
(without panel load)  
L2  
-2.25  
-2.10  
-1.95  
V
V
V
L3  
3•VL1  
-0.1  
4•VL1  
-0.1  
3•VL1  
×0.9  
4•VL1  
×0.9  
-2.25  
100  
L4  
SVD voltage  
SVD  
-2.55  
-2.40  
V
µS  
V
SVD circuit response time  
Analog comparator  
input voltage  
Analog comparator  
offset voltage  
t
SVD  
V
V
V
IP  
Noninverted input (CMPP)  
Inverted input (CMPM)  
V
SS+0.3  
V
DD-0.9  
IM  
OF  
10  
mV  
mS  
Analog comparator  
response time  
t
CMP  
V
IP=-1.5V, VIM=VIP±15mV  
1
Current consumption  
I
I
OP1  
OP2  
During HALT *1  
During operation *1  
During HALT *1  
Without panel load  
OSC1 is crystal oscillation  
Without panel load  
11.5  
14.0  
16.0  
18.7  
33.0  
37.0  
40.5  
44.0  
µA  
µA  
µA  
µA  
During operation *1  
OSC1 is CR oscillation  
1: The SVD circuit and analog voltage comparator are turned OFF.  
E0C62L82 (Normal Operating Mode)  
(Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC1=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL4 are internal voltage, C1–C6=0.1µF)  
Characteristic  
Internal voltage  
Symbol  
Condition  
Min.  
-1.15  
Typ.  
-1.05  
Max.  
-0.95  
Unit  
V
V
V
V
V
V
L1  
Connect 1Mload resistor between VDD and VL1  
(without panel load)  
Connect 1Mload resistor between VDD and VL2  
(without panel load)  
Connect 1Mload resistor between VDD and VL3  
(without panel load)  
Connect 1Mload resistor between VDD and VL4  
(without panel load)  
L2  
2•VL1  
-0.1  
3•VL1  
-0.1  
4•VL1  
-0.1  
-1.30  
2•VL1  
×0.9  
3•VL1  
×0.9  
4•VL1  
×0.9  
-1.10  
100  
V
V
V
L3  
L4  
SVD voltage  
SVD  
-1.20  
V
µS  
V
SVD circuit response time  
Analog comparator  
input voltage  
Analog comparator  
offset voltage  
t
SVD  
V
V
V
IP  
Noninverted input (CMPP)  
Inverted input (CMPM)  
V
SS+0.3  
V
DD-0.9  
IM  
OF  
20  
mV  
mS  
Analog comparator  
response time  
t
CMP  
V
IP=-1.1V, VIM=VIP±30mV  
1
Current consumption  
I
I
OP1  
OP2  
During HALT *1  
During operation *1  
During HALT *1  
Without panel load  
OSC1 is crystal oscillation  
Without panel load  
1.5  
4.0  
6.0  
8.7  
3.0  
7.0  
10.5  
14.0  
µA  
µA  
µA  
µA  
During operation *1  
OSC1 is CR oscillation  
1: The SVD circuit and analog voltage comparator are turned OFF.  
5