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E0C62A81F 参数 Datasheet PDF下载

E0C62A81F图片预览
型号: E0C62A81F
PDF下载: 下载PDF文件 查看货源
内容描述: [4-BIT, MROM, 0.032768MHz, MICROCONTROLLER, PQFP64, PLASTIC, QFP6-64]
分类和应用: 时钟外围集成电路
文件页数/大小: 10 页 / 105 K
品牌: SEIKO [ SEIKO EPSON CORPORATION ]
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E0C6281  
E0C62B81 (Normal Operating Mode)  
(Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC=32.768kHz, Ta=25°C, C  
G
=25pF, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)  
Characteristic  
Internal voltage  
Symbol  
Condition  
Min.  
-1.15  
Typ.  
-1.05  
Max.  
-0.95  
Unit  
V
V
V
V
V
L1  
Connect 1Mload resistor between VDD and VL1  
(without panel load)  
Connect 1Mload resistor between VDD and VL2  
(without panel load)  
Connect 1Mload resistor between VDD and VL3  
(without panel load)  
L2  
2•VL1  
-0.1  
3•VL1  
-0.1  
2•VL1  
×0.9  
3•VL1  
×0.9  
-1.10  
100  
V
V
L3  
SVD voltage  
SVD  
-1.30  
-1.20  
V
µS  
V
SVD circuit response time  
Analog comparator  
input voltage  
Analog comparator  
offset voltage  
t
SVD  
V
V
V
IP  
Noninverted input (CMPP)  
Inverted input (CMPM)  
V
SS+0.3  
V
DD-0.9  
IM  
OF  
20  
mV  
mS  
Analog comparator  
response time  
t
CMP  
V
IP=-1.1V, VIM=VIP±30mV  
3
Current consumption  
I
OP  
During HALT  
During operation *1  
5.5  
7.2  
10.0  
12.0  
µA  
µA  
Without panel load  
1: The SVD circuit and analog voltage comparator are turned OFF.  
E0C62B81 (Heavy Load Protection Mode)  
(Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)  
Characteristic  
Internal voltage  
Symbol  
Condition  
Min.  
-1.15  
Typ.  
-1.05  
Max.  
-0.95  
Unit  
V
V
V
V
V
L1  
Connect 1Mload resistor between VDD and VL1  
(without panel load)  
Connect 1Mload resistor between VDD and VL2  
(without panel load)  
Connect 1Mload resistor between VDD and VL3  
(without panel load)  
L2  
2•VL1  
-0.1  
3•VL1  
-0.1  
2•VL1  
×0.85  
3•VL1  
×0.85  
-1.10  
100  
V
V
L3  
SVD voltage  
SVD  
-1.30  
-1.20  
V
µS  
V
SVD circuit response time  
Analog comparator  
input voltage  
Analog comparator  
offset voltage  
t
SVD  
V
V
V
IP  
Noninverted input (CMPP)  
Inverted input (CMPM)  
V
SS+0.3  
V
DD-0.9  
IM  
OF  
20  
mV  
mS  
Analog comparator  
response time  
t
CMP  
V
IP=-1.1V, VIM=VIP±30mV  
3
Current consumption  
I
OP  
During HALT  
During operation *1  
11.0  
15.0  
20.0  
25.0  
µA  
µA  
Without panel load  
1: The SVD circuit and analog voltage comparator are turned OFF.  
7