E0C5250
■ BLOCK DIAGRAM
BPOUT
CDIN
Data/timing
recovery
circuit
–
INN
INP
FB
Band-pass
filter
FSK
demodulator
SDO
Amp
+
CAS tone
filter
Identification
circuit
Detection
circuit
#DET
VREF
#RDET
#RDRC
RDIN
VDD/2
#PQUAL
#IRQ
VDD
Interrupt
control circuit
To other blocks
VDD
VSS
SDI
Timing
generator
Control circuit
#SCLK
OSC3 OSC4
PDWN #RESET MODE
■ PIN DESCRIPTION
Note: The signal and pin names prefixed by # are those of active-low signals and pins.
Power-down
Pin name Pin No.
Type
Description
state
Off
INP
INN
FB
1
2
Input
Analog
Positive input: Non-inverted amp input
Connect this pin to the RING side of the twisted-pair telephone line through an input-gain
setting resistor and DC-decoupling capacitor. In power-down mode, this pin is
disconnected from the internal circuit.
Input
Analog
Off
Negative input: Inverted amp input
Connect this pin to the TIP side of the twisted-pair telephone line through an input-gain
setting resistor and DC-decoupling capacitor. In power-down mode, this pin is
disconnected from the internal circuit.
3
4
5
6
Output
Analog
High-Z
Amp output
Connect a feedback resistor to set the gain between this pin and the INN pin. In power-
down mode, this pin goes to a high-impedance state.
Reference voltage output
This pin outputs a voltage that is 1/2 of VDD. Connect this pin to VSS via a 0.1-µF
capacitor. In power-down mode, this pin outputs a voltage equal to VDD
Ring detection input
V
REF
Output
Analog
V
DD level
Active
Active
.
RDIN
#RDRC
Schmitt
trigger input
For ring detection, attenuate the ring signal before inputting it to this pin. This input circuit
remains active even in power-down mode.
Open-drain
output
Schmitt
Ring detection RC pin
Connect an RC network to this pin and set the delay time for ring signal detection. This
output circuit remains active even in power-down mode.
trigger input
Output
#RDET
PDWN
7
8
Active
Active
Ring detection output
This pin outputs the #RDRC signal after it is passed through a Schmitt trigger buffer.
Upon detection of the ring signal, this pin changes to Low level.
Power-down input
Input
This pin must be held at Low level during normal operation. When the pin is set to High
level, the E0C5250 is placed in power-down mode. During power-down mode, each pin
on the E0C5250 is placed in the state shown in this table.
2
SEIKO [ SEIKO EPSON CORPORATION ]
