5036 series
PAD LAYOUT
(Unit: µm)
OUT OUTN VCC2 OE
(550, 650)
8
7
6
5
(0,0)
9
TEST
Y
1
2
3
4
(−550, −650)
VCC
XIN XOUT GND
X
Chip size: 1.10 × 1.30mm
Chip thickness: 300 30ꢀm, 180 20ꢀm
PAD size: 150ꢀm × 100ꢀm (VCC, OUT, OUTN pins)
100ꢀm × 100ꢀm (excluding VCC, OUT, OUTN pins)
Chip base: GND potential
Note: The TEST pin is not used during normal operation.
PIN DESCRIPTION and PAD DIMENSIONS
Pad dimensions [µm]
*1
Pad No.
Name
I/O
Function
X
Y
1
2
3
4
VCC
XIN
–
I
(+) supply pin
–390
–39
190
415
–520
–520
–520
–520
Oscillator input pin
Oscillator output pin
(–) ground pin
XOUT
GND
O
–
Output enable pin. Outputs are high impedance when LOW (oscillator
stopped). Power-saving pull-up resistor built-in.
5
OE
I
346
520
6
7
8
9
VCC2
OUTN
OUT
–
O
O
–
(+) output buffer supply pin
Complementary output pin
Output pin
209
–27
520
520
520
28
–306
–414
TEST
IC test pin. Leave open circuit for normal operation.
*1. I: input, O: output
BLOCK DIAGRAM
VCC
XIN
VCC2
OUT
Colpitts
OSC
LV-PECL
1/2
OUTN
XOUT
GND
OE
SEIKO NPC CORPORATION —2
SEIKO [ SEIKO EPSON CORPORATION ]
