CF5019 series
PAD LAYOUT
(Unit: µm)
(900,1050)
Q
VDD
Y
VSS
NPC
INHN
(0,0)
XT XTN
X
Chip size: 0.9 × 1.05mm
Chip thickness: 220µm 30µm
PAD size: 90µm
Chip base: V level
DD
PIN DESCRIPTION and PAD DIMENSIONS
Pad dimensions [µm]
Name
I/O
Description
X
Y
Output state control input. High impedance when LOW (oscillator stops).
Power-saving pull-up resistor built-in.
INHN
I
144.6
190.6
XT
XTN
VSS
Q
I
Amplifier input
347.8
560.6
755.4
755.4
151.4
171
171
Crystal connection pins.
Crystal is connected between XT and XTN.
Amplifier output
O
–
(–) ground
497.8
905.4
918.2
O
–
Output
VDD
(+) supply voltage
BLOCK DIAGRAM
VDD VSS
XTN
XT
C
G
C
D
R
f 1
C
f
RD
R
f 2
Q
INHN
INHN = LOW active
SEIKO NPC CORPORATION —2
SEIKO [ SEIKO EPSON CORPORATION ]
