SA4120A
Mains Crossing Output (FMO)
For best performance the SA4120A also requires an anti-
alias filter on the voltage sense input. Referring to Figure 9,
the capacitor C1 is used to both implement the anti-alias filter
as well as compensating for any phase shift caused by the
current transformer or the shunt resistor. The resistor R4
defines the input current into the device. The optimum input
network is achieved by setting R4 in the order of 100k. If R4
is made too large the capacitor C1 will be very small and the
accuracy of the phase compensation could be affected by
stray capacitances. The potentiometer P1 is used for
calibration purposes.
The FMO pin indicates the polarity of the mains voltage signal
and switches state at the mains voltage zero crossover. Due
to comparator offsets, the duty cycle may not equal exactly
50%. The time between successive rising or falling edges is
equal to the mains period. A microcontroller may use FMO to
extract mains period information. The state of this pin is
undetermined in the absence of a mains voltage. This output
pin is not available on the PDIP8 package option.
TYPICAL APPLICATION
The following description outlines the basic process required
to design a typical single phase energy meter using the
SA4120A and a shunt resistor as a current sensing element.
The meter is capable of measuring 220V/40A/50Hz with a
precision better than Class 1.
OUTPUT SIGNALS
Pulse Output (FOUT)
The average nominal output frequency of the pulse output is
given by
퐼푉 × 퐼퐼 × cos 휙
The most important external circuits required for the
SA4120A are the current input network, the voltage input
network as well as the bias resistor. All resistors should be
1% metal film resistors of the same type to minimize
temperature effects.
푓
= 1160 × |
|
퐹푂푈ꢄ
14 × 16
…(1)
where
IV and II are the analog input currents in µARMS on the voltage
and current sense inputs and
= the phase angle between the current and voltage signals.
Bias Resistor
A bias resistor of R10 = 47k sets optimum bias and
reference currents on chip. Calibration of the meter should be
done using the voltage input and not by means of the bias
resistor.
The integrated anti-creep threshold ensures that no output
pulses are generated if the energy measured is below 0.02%
of FMAX, where FMAX is the output frequency when the voltage
and current channel receive input currents of 14μARMS and
16μARMS respectively. The power-up state of the pulse output
is logic high.
Current Input Network
The voltage drop across the shunt resistor at maximum rated
current should not be less than 5mVRMS and not exceed
100mVRMS. A 320μ shunt is chosen which sets the voltage
drop at maximum rated current to 12.8mV and the maximum
power dissipation in the shunt to 0.5W. The voltage across
the shunt resistor is converted to the required differential
input currents through the current input resistors. Anti-alias
filters are incorporated on these input resistors to filter any
high frequency signal components that could affect the
performance of the SA4120A.
Figure 10 shows the output waveform of FOUT. The output
pulse width tLP is 71μs at nominal on-chip oscillator
frequency. The pulse width doubles in the case of reverse
energy. This allows direct sensing of the energy direction
without using the direction output.
tLP
The four current input resistors (R1, R2, R3, R4) should be of
equal size to optimize the input networks low pass filtering
characteristics, so the values can be calculated as follows:
Figure 10: FOUT pulse output waveform
Direction Output (DIR)
The SA4120A provides information on the direction of energy
flow by means of the direction output. A logic low in the DIR
output means that the device measures negative energy and
a logic high indicates positive energy. The direction output is
only updated with each output pulse. The power-up state of
the DIR output is logic low until the first output pulse is
produced. This output pin is not available on the PDIP8
package option.
ꢆ푆퐻
ꢆ1 = ꢆꢃ = ꢆ3 = ꢆ4 = 퐼푀퐴푋
×
= ꢃ00Ω = ꢆ퐶
4 × 16휇ꢇ
For optimum performance the cut-off frequency of the anti-
alias filter should be between 10kHz and 20kHz. The
equivalent resistance associated with each capacitor is RC/2
so the capacitor values should be in the order of
SPEC-3094 (REV. 2)
29-09-2017
9/14
SAMES [ SAMES ]
